參數(shù)資料
型號: IS42S16100C1-7TI
廠商: INTEGRATED SILICON SOLUTION INC
元件分類: DRAM
英文描述: 512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM
中文描述: 1M X 16 SYNCHRONOUS DRAM, 5.5 ns, PDSO50
封裝: 0.400 INCH, PLASTIC, TSOP2-50
文件頁數(shù): 17/79頁
文件大小: 755K
代理商: IS42S16100C1-7TI
IS42S16100C1
ISSI
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. A
07/21/04
17
CKE RELATED COMMAND TRUTH TABLE
(1)
CKE
n-1
H
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
H
L
Current State
Self-Refresh
Operation
Undefined
Self-Refresh Recovery
(2)
Self-Refresh Recovery
(2)
Illegal
(2)
Illegal
(2)
Self-Refresh
Idle State After t
RC
Has Elapsed
Idle State After t
RC
Has Elapsed
Illegal
Illegal
Power-Down on the Next Cycle
Power-Down on the Next Cycle
Illegal
Illegal
Clock Suspend Termination on the Next Cycle
(2)
Clock Suspend
Undefined
Power-Down Mode Termination, Idle After
That Termination
(2)
Power-Down Mode
No Operation
See the Operation Command Table
Bank Active Or Precharge
Auto-Refresh
Mode Register Set
See the Operation Command Table
See the Operation Command Table
See the Operation Command Table
Self-Refresh
(3)
See the Operation Command Table
Power-Down Mode
(3)
See the Operation Command Table
Clock Suspend on the Next Cycle
(4)
Clock Suspend Termination on the Next Cycle
Clock Suspend Termination on the Next CycleL
n
X
H
H
H
H
L
H
H
H
H
L
L
L
L
H
L
X
H
CS
X
H
L
L
L
X
H
L
L
L
H
L
L
L
X
X
X
X
RAS
X
X
H
H
L
X
X
H
H
L
X
H
H
L
X
X
X
X
CAS
X
X
H
L
X
X
X
H
L
X
X
H
L
X
X
X
X
X
WE
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A11
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A10 A9-A0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Self-Refresh Recovery
Power-Down
L
H
H
H
H
H
H
H
H
H
H
L
H
H
L
L
H
H
H
H
H
L
L
L
L
L
X
H
L
H
L
X
H
L
L
L
L
H
L
L
L
L
X
X
X
X
X
X
X
H
L
L
L
X
H
L
L
L
X
X
X
X
X
X
X
X
H
L
L
X
X
H
L
L
X
X
X
X
X
X
X
X
X
H
L
X
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Both Banks Idle
OP CODE
X
X
X
X
OP CODE
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Other States
Notes:
1. H: HIGH level input, L: LOW level input, X: HIGH or LOW level input
2. The CLK pin and the other input are reactivated asynchronously by the transition of the CKE level from LOW to HIGH.
The minimum setup time (t
CKA
) required before all commands other than mode termination must be satisfied.
3. Both banks must be set to the inactive (idle) state in advance to switch to power-down mode or self-refresh mode.
4. The input must be command defined in the operation command table.
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