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參數(shù)資料
| 型號： | IS41LV16105 |
| 廠商： | Integrated Silicon Solution, Inc. |
| 英文描述： | 1M x 16 DRAM With Fast Page Mode(3.3V,1Mx16帶快速頁模式動態(tài)RAM) |
| 中文描述： | 100萬× 16的DRAM與快速頁面模式（3.3伏，1Mx16帶快速頁模式動態(tài)內(nèi)存） |
| 文件頁數(shù)： | 4/18頁 |
| 文件大?。?/td> | 140K |
| 代理商： | IS41LV16105 |
4
Integrated Silicon Solution, Inc.
—
1-800-379-4774
Rev. A
03/03/00
IS41C16105
IS41LV16105
ISSI
Functional Description
The IS41C16105 and IS41LV16105 is a CMOS DRAM
optimized for high-speed bandwidth, low power applica-
tions. During READ or WRITE cycles, each bit is uniquely
addressed through the 16 address bits. These are entered
ten bits (A0-A9) at a time. The row address is latched by
the Row Address Strobe (
RAS
). The column address is
latched by the Column Address Strobe (
CAS
).
RAS
is
used to latch the first nine bits and
CAS
is used the latter
nine bits.
The IS41C16105 and IS41LV16105 has two
CAS
con-
trols,
LCAS
and
UCAS
. The
LCAS
and
UCAS
inputs
internally generates a
CAS
signal functioning in an iden-
tical manner to the single
CAS
input on the other 1M x 16
DRAMs. The key difference is that each
CAS
controls its
corresponding I/O tristate logic (in conjunction with
OE
and
WE
and
RAS
).
LCAS
controls I/O0 through I/O7 and
UCAS
controls I/O8 through I/O15.
The IS41C16105 and IS41LV16105
CAS
function is deter-
mined by the first
CAS
(
LCAS
or
UCAS
) transitioning
LOW and the last transitioning back HIGH. The two
CAS
controls give the IS41C16105 and IS41LV16105 both
BYTE READ and BYTE WRITE cycle capabilities.
Memory Cycle
A memory cycle is initiated by bring
RAS
LOW and it is
terminated by returning both
RAS
and
CAS
HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum t
RAS
time has expired. A new
cycle must not be initiated until the minimum precharge
time t
RP
, t
CP
has elapsed.
Read Cycle
A read cycle is initiated by the falling edge of
CAS
or
OE
,
whichever occurs last, while holding
WE
HIGH. The
column address must be held for a minimum time speci-
fied by t
AR
. Data Out becomes valid only when t
RAC
, t
AA
,
t
CAC
and t
OEA
are all satisfied. As a result, the access time
is dependent on the timing relationships between these
parameters.
Write Cycle
A write cycle is initiated by the falling edge of
CAS
and
WE
, whichever occurs last. The input data must be valid
at or before the falling edge of
CAS
or
WE
, whichever
occurs last.
Refresh Cycle
To retain data, 1,024 refresh cycles are required in each
16 ms period. There are two ways to refresh the memory.
1. By clocking each of the 1,024 row addresses (A0
through A9) with
RAS
at least once every 16 ms. Any
read, write, read-modify-write or
RAS
-only cycle re-
freshes the addressed row.
2. Using a
CAS
-before-
RAS
refresh cycle.
CAS
-before-
RAS
refresh is activated by the falling edge of
RAS
,
while holding
CAS
LOW. In
CAS
-before-
RAS
refresh
cycle, an internal 9-bit counter provides the row ad-
dresses and the external address inputs are ignored.
CAS
-before-
RAS
is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Power-On
After application of the V
CC
supply, an initial pause of
200 μs is required followed by a minimum of eight
initialization cycles (any combination of cycles contain-
ing a
RAS
signal).
During power-on, it is recommended that
RAS
track with
V
CC
or be held at a valid V
IH
to avoid current surges.
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| IS41LV16256-35K | 256K x 16 (4-MBIT) DYNAMIC RAM WITH EDO PAGE MODE |
| IS41LV16256-35T | 256K x 16 (4-MBIT) DYNAMIC RAM WITH EDO PAGE MODE |
| IS41LV16256-60K | 256K x 16 (4-MBIT) DYNAMIC RAM WITH EDO PAGE MODE |
| IS41LV16256-60KI | 256K x 16 (4-MBIT) DYNAMIC RAM WITH EDO PAGE MODE |
| IS41LV16256-60T | 256K x 16 (4-MBIT) DYNAMIC RAM WITH EDO PAGE MODE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IS41LV16105-50K | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:1M x 16 (16-MBIT) DYNAMIC RAM WITH FAST PAGE MODE |
| IS41LV16105-50KI | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:1M x 16 (16-MBIT) DYNAMIC RAM WITH FAST PAGE MODE |
| IS41LV16105-50T | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:1M x 16 (16-MBIT) DYNAMIC RAM WITH FAST PAGE MODE |
| IS41LV16105-50TI | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:1M x 16 (16-MBIT) DYNAMIC RAM WITH FAST PAGE MODE |
| IS41LV16105-60K | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:1M x 16 (16-MBIT) DYNAMIC RAM WITH FAST PAGE MODE |
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