參數(shù)資料
型號(hào): IS41LV16100
廠商: Integrated Silicon Solution, Inc.
英文描述: 1M x 16 DRAM With EDO Page Mode(3.3V,1Mx16帶擴(kuò)展數(shù)據(jù)輸出頁(yè)模式動(dòng)態(tài)RAM)
中文描述: 100萬(wàn)× 16的DRAM與江戶(hù)頁(yè)面模式(3.3伏,1Mx16帶擴(kuò)展數(shù)據(jù)輸出頁(yè)模式動(dòng)態(tài)內(nèi)存)
文件頁(yè)數(shù): 6/20頁(yè)
文件大?。?/td> 172K
代理商: IS41LV16100
IS41C16100
IS41LV16100
6
Integrated Silicon Solution, Inc.
1-800-379-4774
Rev. F
03/08/00
ISSI
ELECTRICAL CHARACTERISTICS
(1)
(Recommended Operating Conditions unless otherwise noted.)
Symbol
Parameter
Test Condition
Any input 0V
V
IN
Vcc
Other inputs not under test = 0V
Speed
Min.
Max.
Unit
I
IL
Input Leakage Current
–5
5
μA
I
IO
Output Leakage Current
Output is disabled (Hi-Z)
0V
V
OUT
Vcc
–5
5
μA
V
OH
Output High Voltage Level
I
OH
= –5.0 mA (5V)
I
OH
= –2.0 mA (3.3V)
2.4
V
V
OL
Output Low Voltage Level
I
OL
= 4.2 mA (5V)
I
OL
= 2.0 mA (3.3V)
0.4
V
I
CC
1
Standby Current: TTL
RAS
,
LCAS
,
UCAS
V
IH
Commerical
5V
3.3V
5V
3.3V
3
3
4
4
mA
Extended/Industrial
mA
I
CC
2
Standby Current: CMOS
RAS
,
LCAS
,
UCAS
V
CC
– 0.2V
5V
3.3V
2
2
mA
I
CC
3
Operating Current:
Random Read/Write
(2,3,4)
Average Power Supply Current
RAS
,
LCAS
,
UCAS
,
Address Cycling, t
RC
= t
RC
(min.)
-50
-60
160
145
mA
I
CC
4
Operating Current:
EDO Page Mode
(2,3,4)
Average Power Supply Current
RAS
= V
IL
,
LCAS
,
UCAS
,
Cycling t
PC
= t
PC
(min.)
-50
-60
90
80
mA
I
CC
5
Refresh Current:
RAS
-Only
(2,3)
Average Power Supply Current
RAS
Cycling,
LCAS
,
UCAS
V
IH
t
RC
= t
RC
(min.)
-50
-60
160
145
mA
I
CC
6
Refresh Current:
CBR
(2,3,5)
Average Power Supply Current
RAS
,
LCAS
,
UCAS
Cycling
t
RC
= t
RC
(min.)
-50
-60
160
145
mA
Notes:
1. An initial pause of 200 μs is required after power-up followed by eight
RAS
refresh cycles (
RAS
-Only or CBR) before proper device
operation is assured. The eight
RAS
cycles wake-up should be repeated any time the t
REF
refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each EDO page cycle.
5. Enables on-chip refresh and address counters.
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