參數(shù)資料
型號: IRMCK203
廠商: International Rectifier
英文描述: High Performance Sensorless Motion Control IC
中文描述: 高性能運動控制芯片傳感器
文件頁數(shù): 41/57頁
文件大小: 400K
代理商: IRMCK203
IRMCK203
This document is the property of International Rectifier and may not be copied or distributed without expressed consent.
41
Field
Name
DcBusMEnb
Access
(R/W)
Field Description
DC Bus monitor enable. 1 = Monitor DC bus voltage and generate
appropriate brake signal control and disable PWM output when
voltage fault conditions occur. GatekillFlt and OvrSpdFlt faults
cannot be disabled. DC bus voltage thresholds are as follows:
Overvoltage – 410V
Brake On – 380V
Brake Off – 360V
Nominal – 310V
Undervoltage off – 140V
Undervoltage – 120V
This bit clears all active fault conditions. The user should monitor
the FaultStatus read register group to determine fault status and set
this bit to “1” to clear any faults that have occurred. A fault condition
automatically clears the PwmEnbW and FocEnbW bits in the
SystemControl write register group. Note that this bit also directly
controls the output 2137 FLTCLR pin. After clearing a fault, the
user must explicitly set this bit to “0” to re-enable fault processing.
FaultControl Write Register Field Definitions
W
FltClr
W
SystemConfig Register Group (Write Registers)
Byte
Offset
7
0x50
Bit Position
4
6
5
3
2
1
0
ExtCtrl
AdcIfbEnb
Ramp
Stop
SPARE
SystemConfig Write Register Map
Field
Name
RampStop
Access
(R/W)
Field Description
Selects the stopping mode:
0 - Configure for Coast stopping
1 - Configure for Ramp stopping
Selects the current feedback mode:
0 - Selects IR2175 current feedback
1 - Selects Leg-Shunt current feedback
Setting this bit to “1” enables direct control of basic motor operation
via the external User Interface pins. When this bit is “1”, the
FocEnbW and PwmEnbW bits in the SystemControl write register
group are ignored.
SystemConfig Write Register Field Definitions
W
AdcIfbEnb
W
ExtCtrl
W
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