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參數(shù)資料
| 型號(hào)： | IR3Y48 |
| 廠商： | Sharp Corporation |
| 英文描述： | TUBING TEFLON .018 ID 100' CLR |
| 中文描述： | CCD信號(hào)處理 |
| 文件頁數(shù)： | 9/31頁 |
| 文件大?。?/td> | 176K |
| 代理商： | IR3Y48 |
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9
IR3Y48M
CDS
REFIN
CCDIN
S/H
ADIN
OBCAP
(Path for ADIN)
ADCLP
ADCLP
OBP
OBP
Compare
Register (7-bit)
Rough
Fine
DO
0
-
DO
9
AGC
AGC
+
DAC
10-bit
ADC
Black Level Calibration
CCD
ADCK
OBP
OBCAP
Previous
Black Level
Blanking
Blanking
Effective
Pixel Signal
Effective
Pixel Signal
Optical Black Period
Resulting Black
Calibration Level
(Hold)
Black Level Calibration Timing
Black Level Cancel Circuit
The purpose of black level cancel is to adjust the
AGC input level which can equalize the ADC output
code to black level code written in the register. The
black level cancelling is generally done during OB
(optical black period) pulsed by OBP pulse. The
register value ((1 to) 16 to 127 LSB : default 64
LSB) is written by serial interface.
Black level cancel loop is established while OBP is
low (when pulse is not inverted).
In this loop, ADC output code is compared with
register setting. During OB period, the OBP voltage
gradually terminates into certain voltage resulting
the output code equal to the register setting.
The OBP voltage is discharged under following
status :
q
Set black level reset register to 1
w
Set RESET pin low
e
Power down (by STBYN or register control)
The period to reach the final value depends on the
status of chip. It may take more than one thousand
pixels at start-up or after reset. It may take only
several pixels when the status is not changed. DC
clamp [CCDCLP] is allowed during OBP low.
Black level cancelling for ADIN signal (broken line
in the chart) is controlled by ADCLP pulse (clamp
and OB control are done simultaneously) instead of
OBP.
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