參數(shù)資料
型號(hào)： IR3Y48
廠商： Sharp Corporation
英文描述： TUBING TEFLON .018 ID 100' CLR
中文描述： CCD信號(hào)處理
文件頁(yè)數(shù)： 11/31頁(yè)
文件大?。?/td> 176K
代理商： IR3Y48
A/D Converter Circuit
IR3Y48M integrates 20 MHz 10-bit full pipeline A/D
converter (ADC).
A/D CONVERSION RANGE
The analog input range of the ADC is determined
by V
REF
circuit integrated in IR3Y48M. At ADC
direct input (ADIN) mode (Mode (1) Register D
5
=
1), feed 1 Vp-p (full scale) signal based on clamp
level as zero reference into ADIN input pin.
A/D CONVERTER OUTPUT CODE
(AT MODE (1) REGISTER D
5
= 1)
The digital output format is binary.
Thus, "all zero" digital output with zero reference
input (ADIN = CLPCAP), "all one" digital output with
full-scale input (ADIN = CLPCAP + 1 V (TYP.)).
CLOCK, PIPELINE DELAY AND OUTPUT DIGITAL
DATA TIMING
The A/D conversion is performed based on the
clock fed to ADCK pin.
The track-and-hold operation is completed at falling
(when not inverted) edge of ADCK.
The 10-bit width parallel data is obtained at rising
edge after 5.5 clock pipeline delay. (Sampling edge
is selectable by register setting.)
CODE AT CLAMP LEVEL
(AT MODE (1) REGISTER D
5
= 0, D
4
= 1)
The output code at clamp level can be set
throughout (1 to) 16 to 127 LSB at the step of 1
LSB by register setting.
ADC OUTPUT CODE LOGIC
ADC digital output is High-Z under following
conditions :
q
Set ADC output register to 1
w
Set SYBYN pin low
e
Power down (by STBYN or register control)
DIGITAL OUTPUT CODE
According to ADIN, digital codes are determined as
follows :
Data Output at Straight Binary
[Mode (1) Register D
2
= 0, D
5
= 1]
ADIN
11
IR3Y48M
MSB
DIGITAL CODE
LSB
D
9
Clamp
reference
0
:
:
0
:
1
:
Clamp
reference + 1 V
1
1
0
1
0
D
0
1
0
1
0
D
1
1
0
1
0
D
2
1
0
1
0
D
3
1
0
1
0
D
4
1
:
0
1
:
0
D
5
1
0
1
0
D
6
1
0
1
0
D
7
1
0
1
0
D
8
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