參數(shù)資料
型號(hào)： IR3093MTR
廠商： International Rectifier
英文描述： 3 PHASE OPTERON, ATHLON, OR VR10.X CONTROL IC
中文描述： 3相皓龍，速龍，或控制IC的VR10.X
文件頁(yè)數(shù)： 25/39頁(yè)
文件大小： 693K
代理商： IR3093MTR
IR3093
Page 25 of 39
07/15/04
Figure 10 - Temperature compensation of inductor DCR
Remote Voltage Sensing
To compensate for impedance in the ground plane, the VOSNS- pin is used for remote sensing and connects
directly to the load. The VDAC voltage is referenced to VOSNS- to avoid additional error terms or delay related to
a separate differential amplifier. The capacitor connecting the VDAC and VOSNS- pins ensure that high speed
transients are fed directly into the Error Amplifier without delay.
Master-Slave Current Share Loop
Current sharing between phases of the converter is achieved by a Master-Slave current share loop topology. The
output of the Phase 1 Current Sense Amplifier sets the reference for the Share Adjust Error Amplifiers. Each
Share Adjust Error Amplifier adjusts the duty cycle of its respective PWM Ramp and to force its input error to zero
compared to the master Phase 1, resulting in accurate current sharing.
The maximum and minimum duty cycle adjust range of Ramps 2 & 3 compared to Ramp1 has been limited to a
minimum of 0.5x and a maximum of 2.0x typical (see Figure 3.). The crossover frequency of the current share loop
can be programmed with a capacitor at the SCOMPX pin so that the share loop does not interact with the output
voltage loop.
The SCOMPX capacitor is driven by a trans-conductance stage capable of sourcing and sinking 22uA. The duty
cycle of Ramps 2 & 3 inversely tracks the voltage on their
SCOMPX pin; if V(SCOMP2) increases, Ramp2’s slope
will increase and the effective duty cycle will decrease resulting in a reduction in Phase 2’s output current. Due to
the limited 22uA source current, an SCOMPX pre-charge circuit has been included to pre-condition V(SCOMPX)
so that the duty cycle of Ramps 2 & 3 are equal to Ramp1 prior to any GATEHX high pulses. The pre-condition
circuit can source 450uA. The Equal Duty Cycle Comparator (see Block Diagram) activates a pre-charge circuit
when SS/DEL is less than 0.6V. The Error Amplifier becomes active enabling GATEH switching when SS/DEL is
above 1.1V.
Set BIASOUT voltage
BIASOUT pin provides 150mA open-looped regulated voltage for GATE drive bias, and the voltage is set by
SETBIAS
through an external resistor Rset connecting between SETBIAS pin and ground. Bias current I
SETBIAS
is a
function of ROSC. Rset is chosen by equation (15). V
FD
in the equation is the forward voltage drop across the
Bootstrap diode.
VDRP BUFFER
+
IROSC
-
+
ERROR AMPLIFIER
-
VDAC
RFB
RDRP
VDAC
EAOUT
VDRP
VOSNS-
FB
VOUT SENSE+
Current + VDAC
RLINEAR
RNTC
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