參數(shù)資料
型號(hào): IR3093MTR
廠商: International Rectifier
英文描述: 3 PHASE OPTERON, ATHLON, OR VR10.X CONTROL IC
中文描述: 3相皓龍,速龍,或控制IC的VR10.X
文件頁數(shù): 11/39頁
文件大?。?/td> 693K
代理商: IR3093MTR
IR3093
Page 11 of 39
07/15/04
PWM Operation
The IR3093 is a fully integrated 3 phase interleaved PWM control IC which uses voltage mode control with trailing
edge modulation. A high-gain wide-bandwidth voltage type Error Amplifier in the Control IC is used for the voltage
control loop. The PWM block diagram of the IR3093 is shown in Figure 2.
U30
CSINM2
CSINM1
-
+
BB DISABLE
80mV
9p
9p
VDRP BUFFER
+
RESET DOMINANT
RESET DOMINANT
0.47V
IROSC
-
+
PWM COMPARATOR
0 TO IROSC*3/4
+
-
Share Adjust Error Amp
IROSC
-
+
ERROR AMPLIFIER
0.6V
RCS2
RSFF
S
Q
QB
R
CSC2
-
IROSC/2
CCS1
1
2
-
+
PWM COMPARATOR
CCS2
RSC2
RCS1
CCOMP
CDAC
VDAC
-
+
0% DUTY CYCLE
RFB
CLK2
RSFF
S
Q
QB
R
RDRP
RCOMP
RDAC
0.6V
COUT
1
2
VDAC
VDRP
EAOUT
SCOMP2
GATEL1
GATEH1
GATEH2
CSINP1
GATEL2
CSINP2
CSINM3
FB
VOSNS-
VOUT SENSE+
VOUT SENSE-
VOUT-
VOUT+
VDAC
-
+
X23.5
CSINP3
RESET DOMINANT
9p
IROSC
-
+
EAOUT
0 TO IROSC*3/4
+
-
Share Adjust Error Amp
RSFF
S
Q
QB
R
0.6V
RCS3
CCS3
1
2
GATEH3
GATEL3
VIN
CSC3
SCOMP3
RSC3
VIN
VIN
VDAC
-
+
X23.5
VDAC
-
+
X23.5
CLK3
CLK2
CLK1
CLK2
IROSC
CLK3
OSCBLOCK
CLK3
OVPSNS
Figure 2
– PWM Block Diagram
Refer to Figure 3. Upon receiving a clock pulse, the RSFF is set, the internal PWM ramp voltage begins to increase,
the low side driver is turned off, and the high side driver is then turned on. For phase 1, an internal 9pf capacitor is
charged by a current source that proportional to the switching frequency resulting in a ramp rate of 50mV per percent
duty cycle. For example, if the steady-state operating switch node duty cycle is 10%, then the internal ramp amplitude
is typically 500mV from the starting point (or floor) to the crossing of the EAOUT control voltage. When the PWM
ramp voltage exceeds the Error Amplifier’s output voltage, the RSFF is reset. This turns off the high side driver, turns
on the low side driver, and discharges the PWM ramp to 0.6V until the next clock pulse.
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