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| 型號： | IR1155STRPBF |
| 廠商： | International Rectifier |
| 文件頁數(shù)： | 12/21頁 |
| 文件大?。?/td> | 388K |
| 描述： | IC PFC ONE CYCLE CONTROL 8SOIC |
| 特色產(chǎn)品： | International Rectifier - uPFC? Power Factor Correction Ics |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 模式： | 連續(xù)導(dǎo)電（CCM） |
| 頻率 - 開關(guān)： | 可調(diào)式 |
| 電流 - 啟動： | 175µA |
| 電源電壓： | 12 V ~ 19 V |
| 工作溫度： | -25°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | IR1155STRPBFDKR |
IR1155S
www.irf.com
12
?2011 International Rectifier
IR1155 General Description
Programmable Soft Start
The soft start process controls the rate of rise of
the voltage feedback loop error signal thus
providing a linear control on RMS input current
that the PFC converter will admit. The soft start
time is essentially controlled by voltage error
amplifier compensation components selected and
is therefore user programmable to some degree
based on desired loop crossover frequency.
Gate Drive Capability
The gate drive output stage of the IC is a totem
pole driver with 1.5A peak current drive
capability. The gate drive is internally clamped at
13V (Typ). Gate drive buffer circuits can be easily
driven with the GATE pin of the IC to suit any
system power level.
System Protection Features
IR1155 protection features include DC bus
Overvoltage protection (OVP) via a dedicated pin,
Open-loop protection (OLP), Cycle-by-cycle peak
current limit (IPK LIMIT), Soft-current limit and
VCC under voltage lock-out (UVLO).
- Overvoltage voltage protection (OVP) feature in
IR1155 is achieved using a dedicated pin called
the OVP/EN pin. The input of OVP comparator is
connected the OVP pin. When the OVP pin
voltage exceeds V
OVP
, an overvoltage situation is
detected and the gate drive is immediately
terminated. The gate drive is re-enabled only
after OVP pin voltage drops below V
OVP(RST)
. The
use of a dedicated OVP/EN pin ensures that the
system is protected from catastrophic
overvoltages, even if the feed-back loop
(connected to the VFB pin) encounters any
failure. This ensures the best possible system
overvoltage protection against extremes of
situations.
- Open Loop Protection (OLP) is activated
whenever the VFB pin voltage falls below V
OLP
threshold. The gate drive is then immediately
disabled, VCOMP is actively discharged and the
IC is pushed into Stand-by mode. The IC will re-
start (with soft-start) once the VFB pin voltage
exceeds V
OLP
again. There is no voltage
hysteresis associated with this feature. During
start-up the IC is held in Stand-by until this pin
exceeds V
OLP
.
- Soft-current limit is an output voltage fold-back type
protection feature that is encountered when the RMS
current in the PFC converter exceeds a certain
magnitude that causes the internal error signal of the
voltage feedback, V
m
to saturate at its highest value.
Amplitude of V
m
signal is directly proportional to the
RMS input current admitted into the PFC converter.
In effect, once V
m
saturates, the maximum RMS
current admissible into the PFC converter has been
encountered. Any attempt to increase the RMS
current beyond this limit causes the IC to limit the
duty cycle delivered to the PFC converter, which then
has the effect of causing the DC bus voltage to droop
i.e. output voltage folds-back. The current level at
which V
m
saturates is closely related to the value of
the current sense resistor selected for the PFC
converter. In one way, this feature can be perceived
to offer an overpower limitation of sorts at the
conditions at which current sense design is
performed (minimum VAC & maximum output
power). For details, please refer to IR1155
Application Note.
- Cycle-by-cycle peak current limit protection
instantaneously turns-off the gate output whenever
the ISNS pin voltage exceeds V
ISNS(PK)
threshold in
magnitude. The gate drive output is re-enabled only
after the magnitude of the ISNS pin voltage drops
below the V
ISNS(PK)
threshold. It is clarified that even
though the IC operates based on average current
mode control, since the averaging circuit is
decoupled from the peak current limit comparator
input, the IC is still able to provide instantaneous
response to a system overcurrent condition. This
protection feature incorporates a leading edge
blanking circuit following the comparator to improve
noise immunity.
- VCC Under Voltage Lockout protection maintains
the IC in a low current consumption, UVLO mode
during start-up if VCC pin voltage is less than the
VCC turn-on threshold, V
CC,ON
. In UVLO mode the
current consumption is less than I
CC,START
which is
typically about 200uA. Should VCC pin voltage
should drop below UVLO threshold V
CC, UVLO
anytime
after start-up, the IC is pushed back into UVLO mode
(VCOMP pin is discharged) and VCC pin has to
exceed V
CC,ON
again to re-start operation.
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