參數(shù)資料
型號(hào)： IR1155STRPBF
廠商： International Rectifier
文件頁(yè)數(shù)： 11/21頁(yè)
文件大?。?/td> 388K
描述： IC PFC ONE CYCLE CONTROL 8SOIC
特色產(chǎn)品： International Rectifier - uPFC? Power Factor Correction Ics
標(biāo)準(zhǔn)包裝： 1
模式： 連續(xù)導(dǎo)電（CCM）
頻率 - 開(kāi)關(guān)： 可調(diào)式
電流 - 啟動(dòng)： 175µA
電源電壓： 12 V ~ 19 V
工作溫度： -25°C ~ 125°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 8-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 8-SOIC
包裝： 標(biāo)準(zhǔn)包裝
其它名稱(chēng)： IR1155STRPBFDKR
 
IR1155S
 
 
www.irf.com
11 
?2011 International Rectifier
 
IR1155 General Description
 
 
 
 
The 糚FC IR1155 IC is intended for power factor
correction in continuous conduction mode Boost
PFC converters operating at fixed switching
frequency with average current mode control.
The switching frequency is programmable any
where from 48kHz to 200khz. The IC operates
according to IR's proprietary "One Cycle Control"
(OCC) PFC algorithm, which is based on the re-
settable integrator principle. When operating a
AC-DC Boost converter, power factor correction
can be achieved using this algorithm without AC
input line sensing.
 
Theory of Operation
The OCC algorithm works using two loops - a
slow outer voltage loop and a fast inner current
loop. The outer voltage loop monitors the VFB
pin to maintain regulation of boost converter
output voltage and generates a constant error
signal.   The   inner   current   loop   exploits   the
embedded input voltage information in the boost
converter duty cycle to generate a current
reference for power factor correction. The
combination of the two control elements forces
the amplitude and shape of the input current to
be proportional to and in phase with the input
voltage    while    maintaining    output    voltage
regulation. This is true so long as operation in
continuous   conduction   mode   is   maintained.
Average current mode operation is envisaged by
filtering the switching frequency ripple from the
current sense signal in the current loop using an
on-chip filter.
 
The   IC   determines   the   boost   converter
instantaneous   duty   cycle   using   the   voltage
feedback loop error signal V
m
  and the current
sense signal V
ISNS
, which is the voltage at the
current sense pin of the IC. The PWM ramp is
generated using a resettable integrator that
tracks V
m
  every switching cycle. The current
sense signal is amplified by the current amplifier
averaged to remove the ripple component and
fed into the summing node where it is subtracted
from the voltage error signal, V
m
. The resulting
voltage (V
m
  - g
DC
.V
ISNS
) is compared with the
PWM ramp signal by the PWM comparator to
determine   the   gate   drive   duty   cycle.   The
instantaneous duty cycle is mathematically given
by:
D = (V
m
 - g
DC
.V
ISNS
) /V
m
 
A more detailed description of IR1155 theory of
operation is available in Application Note.
Feature set
The IR1155 offers a host of advanced features and
system protections functions, which makes it the
most feature-intensive IC in PFC market in a
compact 8-pin package.
 
User-Programmable Switching Frequency
IR1155   IC   operates   under   fixed   switching
frequency.   The   switching   frequency   is   user-
programmed by inserting a capacitor between
FREQ & COM pins. A pair of current sources inside
the IC source/sink current in/out of the capacitor
alternately thus generating a constant-slope saw-
tooth ramp signal between a pre-determined peak &
valley voltage pair (typically between 2V to 4V). This
saw-tooth signal is the oscillator signal of the IC.
The frequency of operation of the IC can be
programmed anywhere between 48kHz and 200kHz
by suitably sizing the capacitor. The oscillator signal
is a key control signal and is used by the resettable
integrator block of the IC to generate the internal
PWM ramp every switching cycle.
 
IC Supply Circuit & Low start-up current
The IR1155 UVLO circuit maintains the IC in UVLO
mode during start-up if VCC pin voltage is less than
the VCC turn-on threshold, V
CC,ON
  and current
consumption is less than I
CC,START
. Should VCC pin
voltage should drop below UVLO threshold V
CC, UVLO
 
anytime after start-up, the IC is pushed back into
UVLO mode (VCOMP pin is discharged) and VCC
pin has to exceed V
CC,ON
 again to re-start operation.
It is noted that there is no internal clamping of the
VCC pin.
 
User initiated Micropower Sleep mode
The IC can be actively pushed into a micropower
sleep mode where current consumption is less than
I
CC,SLEEP
  by pulling OVP/EN pin below the Sleep
threshold, V
SLEEP(OFF)
, even while VCC is above
V
CC,ON
. This allows the user to disable PFC during
application stand-by situations in order to meet
regulations (Blue Angel, Green Power etc). When
OVP/EN pin is pulled low, the VCOMP pin of the IC
is actively discharged as the IC is relegated to the
Sleep mode. This enables the IC to go through soft-
start when the IC is re-enabled. Since V
SLEEP(OFF)
 is
less than 1V, even logic level signals can be
employed to disable and enable the IC.
 
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