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| 型號： | IQX320-15PP391I |
| 英文描述： | User Programmable Special Function ASIC |
| 中文描述： | 用戶可編程ASIC的特殊功能 |
| 文件頁數(shù)： | 26/65頁 |
| 文件大?。?/td> | 620K |
| 代理商： | IQX320-15PP391I |
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IQX Family Data Sheet
26
Revision 5.0
June 2000
The actual time required to download the configuration bit
streamand programa IQX device depends on the device(s)
used, the user’s specific configuration pattern, and JTAG clock
frequency. Table 11 shows the number of JTAG cycles and
configuration time required for some typical operations. The size
of the memory (number of bytes) required is two (one each for
TDI and TMS) times the number of JTAG cycles divided by eight.
3.3 Configuring Multiple IQX Devices
The JTAG-based controller allows a single device or multiple
IQX devices connected in a chain to be configured in a single
operation. For multiple device configuration, the pins are
connected as shown in Figure 11.
Figure 11. Configuring Multiple IQX Devices
During the initial configuration sequence, the internal controllers
on all IQX devices are first brought to their reset state by pulsing
the TRST*reset pin low. This is followed by the actual
configuration bit stream which is downloaded into the IQX
devices over the TDI and TMS pins.
TDI
IQX
IQX
IQX
U3
U2
U1
TDO
TCK
TMS
TRST*
TDI
TCK
TMS
TRST*
TDO
TDI
TCK
TMS
TRST*
TDO
TDI
TCK
TMS
TRST*
TDO
Operation
IQX320
IQX240B
IQX160
IQX128B
J
C
B
10
bits
84
bits
152
bits
6 KB
J
C
B
10
bits
84
bits
152
bits
4.5
KB
64
bits
692
bits
21 KB 30 K
J
C
B
10
bits
84
bits
152
bits
4 KB
J
C
B
10
bits
84
bits
152
bits
2.5
KB
64
bits
372
bits
6 KB
JTAG Reset Sequence (TMS = “11111”)
5
500
ns
4.2
μ
s
7.6
μ
s
2.4
ms
3.2
μ
s
34.6
μ
s
11.0
ms
13.4
ms
5
500
ns
4.2
μ
s
7.6
μ
s
1.8
ms
3.2
μ
s
34.6
μ
s
8.4
ms
5
500
ns
4.2
μ
s
7.6
μ
s
1.2
ms
3.2
μ
s
18.6
μ
s
3.0
ms
4.2
ms
5
500
ns
4.2
μ
s
7.6
μ
s
1.0
ms
3.2
μ
s
18.6
μ
s
2.4
ms
3.4
ms
Enable or Disable Rapid Configure
42
42
42
42
Change IOB attributes of ONE I/O Port
76
76
76
76
Change IOB attributes of ALL I/O Ports
24 K
18 K
12 K
10 K
Reset JTAG Controller + Reset ALL I/O Ports + Clear ALL SRAM cells
32
64
bits
692
bits
27.5
KB
34 KB 102 K 10.02
32
32
64
bits
372
bits
7.5
KB
11 KB 34 K
32
Connect or disconnect two I/O Ports
346
346
186
186
Configure Entire Switch Matrix
110 K
84 K
24 K
Completely Configure the Device (All I/O and All Switch Matrix Connections) 134K
ms
26 KB 42 K
9 KB
Table 11. Number of JTAG Cycles and Configuration Time (using a 10 MHz JTAG Clock)
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