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參數(shù)資料
| 型號： | IQX320-15PP391I |
| 英文描述： | User Programmable Special Function ASIC |
| 中文描述： | 用戶可編程ASIC的特殊功能 |
| 文件頁數(shù)： | 24/65頁 |
| 文件大?。?/td> | 620K |
| 代理商： | IQX320-15PP391I |
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IQX Family Data Sheet
24
Revision 5.0
June 2000
2.4 Mode Control Register
The IQX device contains a 16-bit Mode Control Register. It
stores the RapidConfigure Enable and certain other non-user
flags which must be set correctly for the proper functioning of the
device. Table 10 shows the bit assignment and their function.
A special JTAG instruction is used to write to the Mode Control
Register. When this register is written using JTAG the least
significant bit (Bit 0) is shifted in first.
Bit #
Name
Default
Description
0
KCNT
0
Key Counter Enable.
When set, uses the internal 5-bit counter to provide
Key Address
1
RM
*
Used to enable IOB configuration through
RapidConfigure interface.
Default value equals the RCE pin value on Reset.
2
RC
*
Enables or disables RapidConfigure mode.
Default value equals the RCE pin value on Reset.
3
IOB_PU1
1
IOB Pull Up 10k Ref
4
BRO_PW1
1
BR external one-shot Pulse Width 10k Ref
5
BRI_PW1
1
BR internal one-shot Pulse Width 10k Ref
6
C_PUMP
1
Charge Pump Enable Bit
7
IOB_PU2
0
IOB Pull Up 20k Ref
8
BRO_PW2
0
BR external one-shot Pulse Width 20k Ref
9
BRI_PW2
0
BR internal one-shot Pulse Width 20k Ref
10
INTERNAL
0
For internal use. Should not be changed by the user.
11
KVAL0
0
Terminal count value bit 0 (LSB) when internal
counter is used as Key Address
12
KVAL1
0
Terminal count value bit 1 when internal counter is
used as Key Address
13
KVAL2
0
Terminal count value bit 2 when internal counter is
used as Key Address
14
KVAL3
0
Terminal count value bit 3 when internal counter is
used as Key Address
15
KVAL4
0
Terminal count value bit 4 (MSB) when internal
counter is used as Key Address
Table 10. Mode Control Register Bit Assignment
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