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| 型號(hào)： | IQX320-15PP391 |
| 英文描述： | User Programmable Special Function ASIC |
| 中文描述： | 用戶可編程ASIC的特殊功能 |
| 文件頁數(shù)： | 10/65頁 |
| 文件大小： | 620K |
| 代理商： | IQX320-15PP391 |
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IQX Family Data Sheet
10
Revision 5.0
June 2000
Figure 3. Switch Matrix Control
1.2 Programmable I/O Port
Each signal line in the Switch Matrix is connected to a
programmable I/O Port. The functional attributes of individual I/O
Ports can be programmed independently. The I/O Port attributes
include its signal direction (in, out or bidirectional), data flow
mode (flow-through, registered or latched), and pull-up current.
Figure 4 shows the structure of the programmable I/O Port. The
sources for the four control signals: clock (CLK), clock enable
(CKE), input enable (IE), and output enable (OE) are also
programmable and are described later in the section “I/O Control
Signals.”
Figure 4. Programmable I/O Port
1.2.1 Programmable Pull-up Current
As shown in Figure 5, the I/O Port contains several n-channel
pull-up devices. The normal pull-up current is supplied by a
device which is switched on/off by internally generated control
signal.
An additional
static
pull-up current (I
PU-WK
) or (I
PU-SG
) can be
programmed at each I/O Port pin. This additional pull-up current
is primarily used for but not restricted to the Bus Repeater (BR)
mode.
Figure 5. IQX Output Driver and Pull-Up Current
1.2.2 Pin and Array Side Trickle Current
N-channel devices are used as a trickle current source
(nomnally 10μA) on the pin side and array side for each I/O
Port. Upon reset, these current sources are turned ON. They
can be turned OFF by configuring the I/O Port.
1.2.3 I/O Port Functional Mode
Table 1 describes the various modes of the I/O Port and the
specification used by the I-Cube Development SystemSoftware
for proper bit streamgeneration.
Legend:
Ax -Switch Matrix Signal
Px -I/O Port Signal
IE -Input Enable
OE -Output Enable
CLK -Clock
CKE - Clock Enable
Column (bit) Address Decoder
R
I/O Port Buffers
I
RA
0
RA
1
RA
m-1
CA
0
CA
1
CA
m-1
Row (word)
Address
Column (bit)
Address
P
i
P
j
(j, i)
(i, j)
I/O Port
BR
CLK
CKE
IE
OE
REG
LAT
REG
E
E
E
E
Delay
E
LAT
CK
Switch
Matrix
CK
NC
NC
PU
PD
A)Pull Down
B)Normal Pull Up
C)Additional Weak Pullup
D)Additional Strong Pullup
D
C
A
B
VDD.PAD
I/O Port
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