參數(shù)資料
型號： IQX128B-7PQ184
英文描述： User Programmable Special Function ASIC
中文描述： 用戶可編程ASIC的特殊功能
文件頁數(shù)： 15/65頁
文件大?。?/td> 620K
代理商： IQX128B-7PQ184
IQX Family Data Sheet
June 2000
Revision 5.0
15
1.3.1 Clock Control
An I/O Port can be individually programmed to select its clock
(CLK) and clock enable (CKE) signals fromsixteen sources. The
source can either be the two (four for IQX320 only) dedicated
pins - GC0 and GC1 (GC0 through GC3 for IQX320), 11 (9 for
IQX320) clock pins that are shared with signal I/O pins - GC2
through GC12 (GC4 through GC12 for IQX320), the nearest
neighboring I/O Port, or the MATCH signal generated using Key
Control (K0 - K4) pins.
1.3.2 Tristate Control
An I/O Port can be individually programmed to select its Input
Enable (IE) and Output Enable (OE) signals fromsixteen
signals. The source can either be the four (five for IQX320 only)
dedicated tristate pins - GT0 through GT3 (GT0 through GT4 for
IQX320), nine (eight for IQX320) tristate pins that are shared
with signal I/O pins - GT4 through GT12 (GT5 through GT12 for
IQX320), the nearest neighboring I/O Port, or the MATCH signal
generated using Key Control (K0 - K4) pins.
1.3.3 Neighboring I/O Port As A Control Source
A physically adjacent I/O Port on the die can be used as a
source for any of the I/O control signals. Port 1 is the control
source for Port 0, Port 2 is the control source for Port 1 and so
on. Port 0 is the control source for the highest number I/O Port
on the device
die
. Note that due to bondout restrictions the
neighboring I/O Port may not always be brought out to a
package pin on the IQX240B and IQX128B devices.
1.3.4 Key Control Pins as a Control Source
The Key Control feature on the IQX devices allows the user to
encode mutually exclusive control signals for use as I/O control
signals. The Key pins, K0 through K4 are shared with I/O Ports.
This feature, shown schematically in Figure 6, works as follows:
Each I/O Port contains a 5-bit
tag
which can be programmed
with a unique value when the I/O Ports are configured. A
comparator in each I/O Port continuously compares the
programmed tag value with the signals present on the Key pins
or the output of the internal 5-bit counter. The output of the
comparator, which produces a logic 1 on a match, can be
selected as a control signal.
The Key Control is intended for use with level sensitive signals
such as IE, OE, CKE (in registered modes only). If Key Control
is used in situations where a short glitch on the internal “Match”
signal is unacceptable (i.e., using the Key Port for CLK in
registered
modes and CLK and/or CKE in
latched
modes), it is
recommended that one of the Key pins be used as a qualifier
and its value changed after the other Key pins have stabilized to
prevent glitches on the internal “Match” signal. Note that when
key match is used as Output Enable (OE) the match will disable
the driver, while a non-match will enable it. This can be reversed
by configuring the I/O Port to use reverse polarity for OE.
Depending on the value of the Counter Enable bit in the Mode
Control Register (see Table 10, the key input to the 5-bit
comparator comes either directly fromthe Key Pins (K0 through
K4) or fromthe output of an internal 5-bit
up
counter. If the
counter is selected by setting the Counter Enable bit to a logic 1,
the Key pins serve as control inputs to the counter as described
below.
K0/KCLK - Counter Clock input
K1/KCKE - Counter Clock Enable
K2/KRST - Counter (Synchronous) Reset
K3/KCLR - Counter (Asynchronous) Clear
K4/K1F - Counter Select “1F” Hex
The counter is a 5-bit modulo up counter controlled by the rising
edge on the counter clock pin (KCLK). It counts up to the 5-bit
value programmed in the Mode Control Register and then resets
to zero on the following clock edge. KCKE pin is used to qualify
the clock. Clocking is enabled when KCKE is high and disabled
when low When the K1F pin is asserted (high), the output of the
counter is forced to “11111” regardless of the internal count.
During this time the counter continues to count up in response to
the clock input. When the KRST pin is asserted, the counter is
reset on the following clock edge. KCLR on the other hand is an
asynchronous clear. When asserted, the counter is immediately
reset to zero. When the device is reset, the Counter Enable bit
and the five Count Value bits are reset to zero.
1.3.5 Default Values for Control Signals
When the device is reset all I/O Ports are set to the default
configuration of flow-through input (IN), This is achieved by
setting the 16-to-1 muxes shown in Figure 6, to select input 15
(V
ss
); while the 2-to-1 muxes used for polarity selections are set
to select non-inverted value for Clock (CLK) and Clock Enable
(CKE), and inverted value for Input Enable (IE) and Output
Enable (OE).
1.4 RapidConfigure (RC) Interface
The RapidConfigure (RC) Interface allows Switch Matrix
connections and I/O Port configurations to be changed quickly. A
single Switch Matrix connection can be made or broken in a
single RapidConfigure cycle; while a single I/O Port or group of
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