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參數(shù)資料
| 型號(hào)： | IQX128B-7PQ184 |
| 英文描述： | User Programmable Special Function ASIC |
| 中文描述： | 用戶可編程ASIC的特殊功能 |
| 文件頁(yè)數(shù)： | 14/65頁(yè) |
| 文件大?。?/td> | 620K |
| 代理商： | IQX128B-7PQ184 |
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IQX Family Data Sheet
14
Revision 5.0
June 2000
1.3 I/O Control Signals
The IQX famly has a structure that gives the user a lot of flexibility in controlling the behavior of each I/O Port. As shown in Figure 6
and described below Clock (CLK), Clock Enable (CKE), Input Enable (IE) and Output Enable (OE) signals for each I/O Port can be
selected frommultiple sources. The control polarity can also be individually selected.
Figure 6. I/O Control
GC0-GC12
13
= Programming Bits
= External Pins
Included in
Each I/O Ports
From Mode
Control Register
0-12
13
14
15
0
1
CKE
X
SEG 3
0-12
13
14
15
0
1
IE
X
SEG 0
0-12
13
14
15
0
1
OE
X
SEG 1
0-12
13
14
15
0
1
CLK
X
SEG 2
C
O
M
P
A
R
E
5-Bit
Tag
Match = 1
5
SEG 4
GT0-GT12
13
Common to
All I/O Ports
COUNTER
5-Bit
Terminal Count
5
0
1
KCLK
KCKE
KRST
KCLR
K0/KCLK
K1/KCKE
K2/KRST
K3/KCLR
K4/K1F
1
0
PORT
X+1
PORT
X
5
Count
K0-K4
5
IOB
X-1
G
G
K
5
IOB
X
IOB
X+1
1 1111
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