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參數(shù)資料
| 型號(hào)： | IQX128B-PQ184 |
| 英文描述： | User Programmable Special Function ASIC |
| 中文描述： | 用戶可編程ASIC的特殊功能 |
| 文件頁數(shù)： | 1/65頁 |
| 文件大?。?/td> | 620K |
| 代理商： | IQX128B-PQ184 |
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IQX Family Data Sheet
June 2000
Revision 5.0
1
F
EATURES
SRAM-based, in-systemprogrammable
Switch Matrix
— Non-Blocking
— Identical and predictable delays
— One-to-one, one-to-many and many-to-one connections
RapidConfigure parallel interface for fast, incremental
configuration of Switch Matrix and I/O Port attributes
— 100% JTAG compliant
Clocked, Latched and Flow-through Dataflow Modes
— As low as 7.5 ns pin-to-pin delay in flow-through mode
and 133 MHz clock rate in registered mode
I/O Ports
— Individually programmable as input, output or
bidirectional
— For each I/O Port, clock, clock enable, input enable and
output enable can be selected independently froma large
pool of common control signals
— 12 mA current drive
— Separated I/O power pins for easy interfacing between
5V and 3.3V signals
D
ESCRIPTION
The IQX famly of SRAM-based bit-oriented switching devices is
manufactured using a 0.6μmCMOS process. These devices
offer clock speeds of up to 133 MHz and pin-to-pin delay as low
as 7.5 ns.
The IQX devices are used in applications requiring dynamc
switching and flexible routing / interconnection of signals. These
applications include communication switches, network systems,
DSP / image processing engines and file/video servers.
At the heart of IQX devices is a non-blocking Switch Matrix. A
line in the Switch Matrix can be connected to one or more other
lines. The Switch Matrix lines are connected to I/O Ports with
programmable functional attributes.
The RapidConfigure parallel interface allows connections in the
Switch Matrix to be changed quickly and incrementally. This
interface can also be used to configure I/O Port attributes
individually and incrementally. In either case, data integrity is
maintained on all unchanged signal paths through the device.
The IQX devices support the industry standard JTAG (IEEE
1149.1) interface for boundary scan testing. The same interface
can also used for serially downloading the configuration bit
streaminto the devices.
Figure 1. IQX Functional Block Diagram
I/O Port
I/O
Control
Switch Matrix
[Crossbar Array]
JTAG Configuration Control
Signal
Ports
TDI TMS TCK
TDO
I/O Port
I/O Port
RapidConfigure
Interface
I/O Port
I/O Port
I/O Port
I/O Port
Shared with
I/O Control
Signals
Dedicated
I/O Control Signals
TRST*
Shared with
RapidConfigure
Interface Signals
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