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參數(shù)資料
| 型號(hào)： | IPM6220CB |
| 英文描述： | Analog IC |
| 中文描述： | 模擬IC |
| 文件頁數(shù)： | 7/15頁 |
| 文件大?。?/td> | 343K |
| 代理商： | IPM6220CB |
7
can be changed on-the-fly with programmable slew rate,
which makes it especially suitable for the processors that
feature modern power savings techniques as SpeedStep
TM
or PowerNow!
TM
.
Both, core and I/O converters can operate in two modes:
fixed frequency PWM and variable frequency hysteretic
depending on the load level. At loads lower than the critical
where filter inductor current becomes discontinuous,
hysteretic mode of operation is activated. Switchover from
PWM to hysteretic operation at light loads improves the
converters' efficiency and prolongs battery run time. In
hysteretic mode, comparators are synchronized to the main
clock that allows seamless transition between the
operational modes and reduced channel-to-channel
interaction. As the filter inductor resumes continuous
current, the PWM mode of operation is restored.
The core converter incorporates Intersil's proprietary output
voltage droop for optimum handling of fast load transients
found in modern processors. The droop is compensated for
the processor mode changes, which allows for relatively
equal droop in any operation mode and to specify the droop
as a fraction of the VID set voltage.
Initialization
The IPM6210 initializes upon receipt of input power
assuming EN is high or not connected. The Power-On Reset
(POR) function continually monitors the input supply voltage
on the VCC pin and initiates soft-start operation after input
supply voltage exceeds 4.5V. Should this voltage drop lower
than 4.0V, POR disables the chip.
Soft-Start
When soft start is initiated, the voltage on the SOFT pin
starts to ramp gradually due to the 25
μ
A current sourced into
the external capacitor.
When SOFT-pin voltage reaches 0.9V, the value of the
sourcing current rapidly changes to 500
μ
A charging the soft-
start capacitor to the level determined by the DAC. This
completes the soft start sequence, Figure 1. As long as the
SOFT voltage is above 0.9V, the maximum value of the
internal soft-start current is set to 500
μ
A allowing fast rate-of-
change in the core output voltage due to a VID code change.
In this mode SOFT has both sourcing and sinking
capabilities to maintain voltage across the soft-start
capacitor conforming to the VID code.
This dual slope approach helps to provide safe rise of
voltages and currents in the converters during initial start-up
and at the same time sets a controlled speed of the core
voltage change when the processor commands to do so.
Soft-start circuits for the I/O converter is slaved to the core
output soft-start circuit and they complete their ramp-up
when voltage on the SOFT pin reaches 0.9V.
The value of the soft-start capacitor can be estimated by the
following equation:
For the typical conditions when DVdac = 0.25V, Dt = 100
μ
s:
With this value of the soft-start capacitor, soft start time will
be equal to:
OUT1 Voltage Program
This output of PWM1 converter is designated to supply the
microprocessor core voltage. The OUT1 voltage is
programmed to discrete levels between 0.925V
DC
and
2.0V
DC
as specified in Table 1. The voltage identification
(VID) pins program an internal voltage reference (DAC)
through a TTL-compatible 5-bit digital-to-analog converter.
The level of the DAC voltage also sets the PGOOD, UVP and
OVP thresholds. The VID pins can be left open for a logic 1
input due to internal 1
μ
A pull-up to V
CC
.
The ‘11111’ and ‘0111‘ VID codes, as shown in Table 1, shut
the IC down and set PGOOD low.
Core Converter PWM Operation
At the nominal current core converter operates in a fixed
frequency PWM mode. The output voltage is compared with
a reference voltage set by the DAC. The derived error signal
is amplified by an internally compensated error amplifier and
applied to the inverting input of the PWM comparator. To
provide output voltage droop for enhanced dynamic load
regulation, a signal proportional to the output current is
added to the voltage feedback signal. This feedback scheme
in conjunction with a PWM ramp proportional to the input
voltage allows for fast and stable loop response over a wide
range of input voltage and output current variations. For the
sake of efficiency and maximum simplicity, the current sense
signal is derived from the voltage drop across the lower
MOSFET during its conduction time.
FIGURE 1. INITIAL STARTUP
Ch3 V
CLK
1.0V
Ch2 V
IO
500mV
Ch4 V
EN
5.0V
M1.00ms
V
IN
= 20V
Ch1 V
CPU
500mV
1
2
3
4
Css
------------------
t
=
Css
-------------------
100
μ
s
0.2
μ
F
=
=
Tss
--------------------------------
7.2ms
=
=
IPM6210
SpeedStep is a trademark of Intel Corporation.
PowerNow! is a trademark of Advanced Micro Devices, Inc.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IPM6220EVAL1 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Advanced Triple PWM Only Mode and Dual Linear Power Controller for Portable Applications |
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| IPM-C114 | 制造商:JDSU 制造商全稱:JDS Uniphase Corporation 功能描述:Miniature Integrated Power Monitor |
| IPM-C122 | 制造商:JDSU 制造商全稱:JDS Uniphase Corporation 功能描述:Miniature Integrated Power Monitor |
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