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參數(shù)資料
| 型號(hào)： | IPM6220ACAZ-T |
| 廠商： | Intersil |
| 文件頁數(shù)： | 9/15頁 |
| 文件大?。?/td> | 527K |
| 描述： | IC REG 5OUT BUCK/LDO SYNC 24SSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 拓?fù)洌?/td> | 降壓（降壓）同步（3），線性（LDO）（2） |
| 功能： | 任何功能 |
| 輸出數(shù)： | 5 |
| 頻率 - 開關(guān)： | 300kHz |
| 電壓/電流 - 輸出 1： | 控制器 |
| 電壓/電流 - 輸出 2： | 控制器 |
| 電壓/電流 - 輸出 3： | 控制器 |
| 帶 LED 驅(qū)動(dòng)器： | 無 |
| 帶監(jiān)控器： | 無 |
| 帶序列發(fā)生器： | 是 |
| 電源電壓： | 5.6 V ~ 24 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | * |
| 封裝/外殼： | * |
| 供應(yīng)商設(shè)備封裝： | * |
| 包裝： | * |
9
3.3V Main and 5V Main Soft Start, Sequencing and
Stand-by
See Table 1 for the output voltage control algorithm. The 5V
Main and 3.3V Main converters are enabled if SDWN1
and
SDWN2
are high and SDWNALL
is also high. The stand-by
mode is defined as a condition when SDWN1
and SDWN2
are
low and the PWM converters are disabled but SDWNALL
is
high (3.3V ALWAYS and 5V ALWAYS outputs are enabled). In
this power saving mode, only the low power micro-controller
and keyboard may be powered.
Soft start of the 3.3V Main and 5V Main converters is
accomplished by means of capacitors connected from pins
SDWN1
and SDWN2
to ground. In conjunction with 5礎(chǔ)
internal current sources, they provide a controlled rise of the
3.3V Main and 5V Main output voltages. The value of the
soft-start capacitors can be calculated from the following
expression.
Where Tss
is the desired soft-start time.
By varying the values of the soft-start capacitors, it is possible
to provide sequencing of the main outputs at startup.
Figure 7 shows the soft-start initiated by the SDWNALL
pin
being pulled high with the Vbatt input at 10.8V and the
resulting 3.3V Main and 5V Main outputs.
While the SDWNALL
pin is held low, prior to T0, all outputs
are off. Pulling SDWNALL
high enables the 3.3V ALWAYS
and 5V ALWAYS outputs. With the 3.3V Main and 5V Main
outputs enabled, at T1, the internal 5礎(chǔ) current sources start
charging the soft start capacitors on the SDWN1
and
SDWN2
pins. At T2 the outputs begin to rise and because
they both have the same value of soft-start capacitors,
0.022礔, they both reach regulation at the same time, T3.
The soft-start capacitors continue to charge and are
completely charged at T4.
12V Converter Architecture
The 12V boost converter generates its output voltage from
the 5V Main output. An external MOSFET, inductor, diode
and capacitor are required to complete the circuit. The
output signal is fed back to the controller via an external
resistive divider. The boost controller can be disabled by
connecting the VSEN3 pin to 5V ALWAYS.
The control circuit for the 12V converter consists of a 3:1
frequency divider which drives a ramp generator and resets
a PWM latch as shown in Figure 8. The width of the CLK/3
pulses is equal to the period of the main clock, limiting the
duty cycle to 33%. The output of a non-inverting error
amplifier is compared with the rising ramp voltage. When the
ramp voltage becomes higher than the error signal, the
PWM comparator sets the latch and the output of the gate
driver is pulled high providing leading edge, voltage mode
PWM. The falling edge of the CLK/3 pulses resets the latch
and pulls the output of the gate driver low.
TABLE 1. OUTPUT VOLTAGE CONTROL
SDWNALL SDWN1 SDWN2
3V AND 5V
ALWAYS 5V MAIN 3V MAIN
0
X
X
OFF
OFF
OFF
1
0
0
ON
OFF
OFF
1
1
0
ON
ON
OFF
1
0
1
ON
OFF
ON
1
1
1
ON
ON
ON
Css
5礎(chǔ) Tss
?/DIV>
3.5V
--------------------------- -
=
SDWN2, 2V/DIV.
3.3V
OUT
, 2V/DIV.
5V
OUT
, 2V/DIV.
0V
0V
4ms/DIV.
SDWN1, 2V/DIV.
T0 T1 T2
T3 T4
SDWNALL
,10V/DIV.
V
IN
= 10.8V
FIGURE 7. SOFT-START ON 3.3V AND 5V OUTPUTS
IPM6220A
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