參數(shù)資料
型號(hào)： IPM6220ACAZ-T
廠商： Intersil
文件頁(yè)數(shù)： 4/15頁(yè)
文件大?。?/td> 527K
描述： IC REG 5OUT BUCK/LDO SYNC 24SSOP
標(biāo)準(zhǔn)包裝： 2,500
拓?fù)洌?/td> 降壓（降壓）同步（3），線性（LDO）（2）
功能： 任何功能
輸出數(shù)： 5
頻率 - 開(kāi)關(guān)： 300kHz
電壓/電流 - 輸出 1： 控制器
電壓/電流 - 輸出 2： 控制器
電壓/電流 - 輸出 3： 控制器
帶 LED 驅(qū)動(dòng)器： 無(wú)
帶監(jiān)控器： 無(wú)
帶序列發(fā)生器： 是
電源電壓： 5.6 V ~ 24 V
工作溫度： -40°C ~ 85°C
安裝類型： *
封裝/外殼： *
供應(yīng)商設(shè)備封裝： *
包裝： *
4
Absolute Maximum Ratings
Thermal Information
Input Voltage, VBATT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +27.0V
Phase, ISEN and SDWNALL
 Pins. . . . . . . . . . .GND -0.3V to +27.0V
Boot and UGATE Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +33.0V
BOOT1, 2 with Respect to PHASE1, 2 . . . . . . . . . . . . . . . . . . . +6.5V
All Other Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.5V
Operating Conditions
Input Voltage, VBATT . . . . . . . . . . . . . . . . . . . . . . . .+5.6V to +24.0V
Ambient Temperature Range. . . . . . . . . . . . . . . . . . . .-10癈 to 85癈
Junction Temperature Range. . . . . . . . . . . . . . . . . . . . 0癈 to 125癈
Thermal Resistance (Typical, Note 1)
?/DIV>
JA
 (癈/W)
SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
110
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150癈
Maximum Storage Temperature Range. . . . . . . . . . .-65癈 to 150癈
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300癈
(SSOP - Lead Tips Only)
CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. ?/DIV>
JA
 is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications    Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System 
Diagrams, and Typical Application Schematic
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP    MAX
UNITS
Input Quiescent Current
I
CC
SDWN1
 = SDWN2
 = 5V, SDWNALL
 = VIN,
Outputs open circuited
-
1.4
2.0
mA
Stand-by Current
I
CCSB
SDWN1
 = SDWN2
 = 0V, SDWNALL
 = VIN,
Outputs open circuited
-
300
礎(chǔ)
Shut-down Current
I
CCSN
SDWNALL
 = 0V
-
<1.0
礎(chǔ)
Input Under-voltage Lock Out
UVLO
Rising VBATT
4.3
4.7
5.1
V
Input Under-voltage Lock Out
UVLO
VBATT, Hysteresis
300
mV
OSCILLATOR
PWM1,2 Oscillator Frequency
F
c1,2
255
300
345
kHz
REFERENCE AND SOFT START
Internal Reference Voltage
V
REF
-
2.472
-
V
Reference Voltage Accuracy
-1.0
-
+1.0
%
SDWN1, SDWN2 Output Current During
Start-up
I
SS
-
5
-
礎(chǔ)
PWM1 CONVERTER, 5V Main
Output Voltage
V
OUT1
 
5.0
V
Line and Load Regulation
0.0 < IVOUT1 < 5.0A; 5.6V < VBATT < 22.0V
-2
0.5
+2
%
Under-Voltage Shut-Down Level
V
UV1
2祍 delay, % Feedback Voltage at VSNS1 pin
70
75
80
%
Current Limit Threshold
I
OC2
Current from ISNS1 Pin Through RSNS1
90
135
180
礎(chǔ)
Over-Voltage Threshold
V
OVP1
2祍 delay, % Feedback Voltage at VSNS1 pin
110
115
120
%
Maximum Duty Cycle
DC
MAX
SDWN1 > 4.0V
94
%
PWM2 CONVERTER, 3.3V Main
Output Voltage
VOUT2
3.3
V
Line and Load Regulation
0.0 < IVOUT2 < 5.0A; 5.6V < VBATT < 24.0V
-2
0.5
+2
%
Under-Voltage Shut-Down Level
V
UV2
2祍 delay, % Feedback Voltage at VSNS2 pin
70
75
80
%
Current Limit Threshold
I
OC2
Current from ISNS2 Pin Through RSNS2
90
135
180
礎(chǔ)
Over-Voltage Threshold
V
OVP2
2祍 delay, % Feedback Voltage at VSNS2 pin
110
115
120
%
Maximum Duty Cycle
DC
MAX
SDWN2 > 4.0V
94
%
Internal Resistance to GND on VSNS2 Pin
R
VSNS2
66K
&
IPM6220A
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