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參數(shù)資料
| 型號： | IPD2548A |
| 元件分類： | 顯示用LED |
| 英文描述： | 5X7 DOT MATRIX DISPLAY, YELLOW, 6.4 mm |
| 封裝： | ROHS COMPLIANT, HERMETIC SEALED, CERAMIC PACKAGE-20 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 869K |
| 代理商： | IPD2548A |
2006-03-03
6
IPD2545A, IPD2547A, IPD2548A
Notes:
1)
Wait 1.0 ms between any Reads or Writes after writing a Control Word with a Clear (D7=1). Wait 1.0 s between any Reads or Writes
after Clearing a Control Word with a Clear (D7=0). All other Reads and Writes can be back to back.
2)
All input voltages are (V
IL=0.8 V, VIH=2.0 V)
3)
Data out voltages are measured with 100 pF on the data bus and the ability to source = –40 A and sink=1.6 mA The rise and fall times
are 60 ns. V
OL=0.4 V, VOH=2.4 V.
Switching Specifications (V
CC=4.5 V)
Write Cycle Timing
Parameter
Description
Specification Minimum
–55
°C
+25
°C
+100
°C
Units
T
CLR
(1)
Clear RAM
1.0
s
T
CLRD
(1)
Clear RAM Disable
1.0
s
T
AS
Address Setup
10
ns
T
CES
Chip Enable Setup
0
ns
T
RS
Read Enable Setup
10
ns
T
DS
Data Setup
20
30
50
ns
T
W
Write Pulse
60
70
90
ns
T
AH
Address Hold
20
30
40
ns
T
DH
Data Hold
20
30
40
ns
T
CEH
Chip Enable Hold
0
ns
T
RH
Read Enable Hold
20
30
40
ns
T
ACC
Total Access Time = Setup Time + Write
Time + Hold Time
90
110
140
ns
Switching specifications (V
CC=4.5 V)
Read Cycle Timing
Parameter
Description
Specification Minimum
–55
°C
+25
°C
+100
°C
Units
T
AS
Address Setup
0
ns
T
CES
Chip Enable
0
ns
T
WS
Write Enable Setup
20
30
40
ns
T
DD
Data Delay Time
100
150
175
ns
T
R
Read Pulse
150
175
200
ns
T
AH
Address Hold
0
ns
T
DH
Data Hold
0
ns
T
TRI
Time to Tristate (Max. time)
30
40
50
ns
T
CEH
Chip Enable Hold
0
ns
T
WH
Write Enable Hold
30
40
50
ns
T
RACC
Total Access Time = Setup Time + Read
Time + Time to Tristate
200
245
290
ns
T
WAIT
(1)
Wait Time between Reads
0
ns
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