參數(shù)資料
型號(hào)： IQ32B-TQ52
元件分類(lèi)： 數(shù)字信號(hào)處理外設(shè)
英文描述： CROSSBAR SWITCH, PQFP52
封裝： PLASTIC, TQFP-52
文件頁(yè)數(shù)： 1/31頁(yè)
文件大?。?/td> 620K
代理商： IQ32B-TQ52
IQ Family Data Sheet
January 1999
1
FEATURES
SRAM-based, in-system programmable
Switch Matrix
— Non-Blocking
— Identical and predictable delays
— One-to-one, one-to-many and many-to-one connections
RapidConnect parallel interface for fast, incremental
conguration of Switch Matrix and I/O Port attributes
— 100% JTAG compliant
— Pin compatible with the IQX family of devices
Clocked, Latched and Flow-through Dataow Modes
— As low as 7 ns pin-to-pin delay in ow-through mode and
150 MHz clock rate in registered mode
I/O Ports
— Individually programmable as input, output or bidirectional
— For each I/O Port, clock, clock enable, input enable and
output enable can be selected independently from a large
pool of common control signals
— 12 mA current drive
— Separated I/O power pins for easy interfacing between 5V
and 3.3V signals
DESCRIPTION
The IQ family of SRAM-based bit-oriented switching devices is
manufactured using 0.6m CMOS processes. These devices
offer clock speeds of up to 150 MHz and pin-to-pin delay as low
as 7 ns.
The IQ devices are used in applications requiring dynamic
switching and exible routing /interconnection of signals. These
applications include communication switches, network systems,
image processing engines, le/video servers, testers and
emulators.
At the heart of IQ devices is a non-blocking Switch Matrix. A line
in the Switch Matrix can be connected to one or more other
lines. The Switch Matrix lines are connected to I/O Ports with
programmable functional attributes.
The Switch Matrix connections are programmed and the I/O Port
attributes are congured by storing data in the internal SRAM
cells. The IQ devices use a JTAG-based serial mode for
conguration. For dynamic switching, the RapidConnect interface
allows fast connection changes.
The IQ devices support the industry standard JTAG (IEEE
1149.1) interface for boundary scan testing. The same interface
is also used for serially downloading the conguration bit stream
into the devices.
Pn-1
Pn-m
(OE0-OE3)
Clocking
Control
Switch Matrix
[Crossbar Array]
Configuration
Control
Signal
Ports
Signal or
RapidConnect
Control Ports
TDI
TMS
TCK
TDO
P0
P1
(ICLK, OCLK)
Output
Enable
TRST*
Figure 1. IQ Functional Block Diagram
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