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參數(shù)資料
| 型號： | IPD2548A |
| 元件分類： | 顯示用LED |
| 英文描述： | 5X7 DOT MATRIX DISPLAY, YELLOW, 6.4 mm |
| 封裝： | ROHS COMPLIANT, HERMETIC SEALED, CERAMIC PACKAGE-20 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 869K |
| 代理商： | IPD2548A |
IPD2545A, IPD2547A, IPD2548A
2006-03-03
5
Pin Definitions
Pin
Function
Definition
Pin
Function
Definition
1
RD
Active low, will enable a processor to
read all registers.
11
WR
Write. Active low. If the device is
selected, a low on the write input loads
the data into memory.
2
CLK I/O
If CLK SEL (pin 3) is low, then expect an
external clock source into this pin. If CLK
SEL is high, then this pin will be the
master or source for all other devices
which have CLK SEL low.
12
D7
Data Bus bit 7 (MSB).
3
CLKSEL
CLocK SELect determines the action of
pin 2, CLK I/O. See section on
Cascading for an example.
13
D6
Data Bus bit 6.
4
RST
Reset. The Reset pulse should be less
than 1 ms. Reset is used only to
synchronize blinking and will not clear
the display.
14
D5
Data Bus bit 5.
5
CE1
Chip enable (active high).
15
D4
Data Bus bit 4.
6
CE0
Chip enable (active low).
16
D3
Data Bus bit 3.
7
A2
Address input (MSB).
17
D2
Data Bus bit 2.
8
A1
Address input.
18
D1
Data Bus bit 1.
9
A0
Address input (LSB).
19
D0
Data Bus bit 0 (LSB).
10
GND
Ground.
20
V
CC
Positive power pin.
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