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參數(shù)資料
| 型號： | IPD2132 |
| 元件分類： | 顯示用LED |
| 英文描述： | 5X7 DOT MATRIX DISPLAY, HIGH EFFICIENCY RED, 4.8 mm |
| 封裝： | ROHS COMPLIANT PACKAGE-32 |
| 文件頁數(shù)： | 3/16頁 |
| 文件大小： | 960K |
| 代理商： | IPD2132 |
IPD2131, IPD2132, IPD2133
2006-04-04
11
Character RAM
The Character RAM is selected when FL, A4 and A3 are set to
1,1,1 during a read or write cycle. The Character RAM is a 8 by 8
bit RAM with each of the eight locations corresponding to a digit on
the display. Digit 0 is on the left side of the display and digit 7 is on
the right side of the display. Address lines, A2–A0 select the digit
address with A2 being the most significant bit and A0 being the
least significant bit. The two types of data stored in the Character
RAM are the ASCII coded data and the UDC Address Data. The
type of data stored in the Character RAM is determined by data bit,
D7. If D7 is low, then ASCII coded data is stored in data bits D6–
D0. If D7 is high, then UDC Address Data is stored in data bit D3–
D0.
The ASCII coded data is a 7 bit code used to select one of 128
ASCII characters permanently stored in the ASCII ROM.
The UDC Address data is a 4 bit code used to select one of the
UDC characters in the UDC RAM. There are up to 16 characters
available. See Table Character RAM Access Logic“ (page 11).
UDC Address Register and UDC RAM
The UDC Address Register and UDC RAM allows the user to gen-
erate and store up to 16 custom characters. Each custom charac-
ter is defined in 5 x 7 dot matrix pattern. It takes 8 write cycles to
define a custom character, one cycle to load the UDC Address
Register and 7 cycles to define the character. The contents of the
UDC Address Register will store the 4 bit address for one of the 16
UDC RAM locations. The UDC RAM is used to store the custom
character.
UDC Address Register
The UDC Address Register is selected by setting FL=1, A4=0,
A3=0. It is a 4 bit register and uses data bits, D3–D0 to store the
4 bit address code (D7–D4 are ignored). The address code
selects one of 16 UDC RAM locations for custom character gen-
eration.
UDC RAM
The UDC RAM is selected by setting FL=1, A4=0, A3=1. The RAM
is comprised of a 7 x 5 bit RAM. As shown in Table UDC Charac-
ter Map“ (page 12), address lines, A2-A0 select one of the 7 rows
of the custom character. Data bits, D4-D0 determine the 5 bits of
column data in each row. Each data bit corresponds to a LED. If
the data bit is high, then the LED is on. If the data bit is low, the
LED is off. To create a character, each of the 7 rows of column
data need to be defined. See Tables UDC Address Register and
logic.
Flash RAM
The Flash RAM allows the display to flash one or more of the char-
acters being displayed. The Flash Ram is accessed by setting FL
low. A4 and A3 are ignored. The Flash RAM is a 8 x 1 bit RAM with
each bit corresponding to a digit address. Digit 0 is on the left side
of the display and digit 7 is on the right side of the display. Address
lines, A2–A0 select the digit address with A2 being the most signif-
icant digit and A0 being the least significant digit. Data bit, D0, sets
and resets the flash bit for each digit. When D0 is high, the flash bit
is set; and when D0 is low, it is reset. See Table Flash RAM
Access Logic“ (page 12).
Character RAM Access Logic
RST
CE
WR
RD
FL
A4
A3
A2
A1
A0
D7 D6 D5 D4 D3 D2 D1 D0
1
0
1
Character Address for
Digits 0–7
0
7 bit ASCII code for a Write Cycle
1
0
1
0
1
Character Address for
Digits 0–7
0
7 bit ASCII code read during a Read Cycle
1
0
1
0
Character Address for
Digits 0–7
1
D3–D0=UDC address for a Write Cycle
1
0
1
0
1
0
Character Address for
Digits 0–7
1
D3–D0=UDC address for Read Data
UDC Address Register and UDC Character RAM
RST
CE
WR
RD
FL
A4
A3
A2
A1
A0
D7 D6 D5 D4 D3 D2 D1 D0
1
0
1
0
Not used for UDC
Address Register
D3–D0=UDC RAM Address Code
for Write Cycle
UDC
Address
Register
1
0
1
0
1
0
Not used for UDC
Address Register
D3–D0=UDC RAM Address Code
for Read Cycle
1
0
1
0
1
A2–A0=Character
Row Address
D4–D0=Character Column Data
for Write Cycle
UDC
RAM
1
0
1
0
1
0
1
A2–A0=Character
Row Address
D4–D0=Character Column Data
read during a Read Cycle
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