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參數(shù)資料
| 型號： | IPD2132 |
| 元件分類： | 顯示用LED |
| 英文描述： | 5X7 DOT MATRIX DISPLAY, HIGH EFFICIENCY RED, 4.8 mm |
| 封裝： | ROHS COMPLIANT PACKAGE-32 |
| 文件頁數(shù)： | 15/16頁 |
| 文件大?。?/td> | 960K |
| 代理商： | IPD2132 |
2006-04-04
8
IPD2131, IPD2132, IPD2133
Character Set
Notes: 1. Upon power up, the device will initialize in a random state.
2.
X=don’t care.
Cascading Diagram
Cascading Displays
The display’s oscillator is designed to drive up to 16 other display’s with input loading of 15 pF each.
The following are the general requirements for cascading 16 displays together:
Determine the correct address for each display.
Use CE from an address decoder to select the correct display.
Select one of the Displays to provide the Clock for the other
displays. Connect CLKSEL to V
CC for this display.
Tie CLKSEL to ground on other displays.
Use RST to synchronize the blinking between the displays.
IDCS5086
ASCII
CODE
D0
D1
D2
D3
HEX
D4
D5
D7
LL
L
0
1
H
L
2
LH L
3
LH H
4
LL
L
5
LL H
6
LH L
7
LH H
L
0
1
L
H
L
2
L
H
3
L
H
4
L
H
L
5
L
H
L
6
L
H
L
H
7
L
H
8
H
L
9
H
L
H
L
A
H
L
H
B
H
L
H
C
H
L
D
H
L
E
H
L
H
F
H
D6
L
H
HX
XX
8
UDC
0
UDC
1
UDC
2
UDC
3
UDC
4
UDC
5
UDC
6
UDC
7
UDC
8
UDC
9
UDC
10
UDC
11
UDC
12
UDC
14
UDC
15
13
UDC
IDCD5031
RD
WR
FL
CLK CLK
Display
CC
V
D0-D7 A0-A4
CE
Up to 14 more
displays in between
I/O
SEL
CE
Display
D0-D7 A0-A4
Data I/O
Address
Decoder
Address
Address Decode Chip 1 to 14
A6
A7
A9
WR
FL
RST
0
15
RD
RST
RD
WR
FL
CLK
SEL
CLK
I/O
A8
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