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參數(shù)資料
| 型號： | IPD2131 |
| 元件分類： | 顯示用LED |
| 英文描述： | 5X7 DOT MATRIX DISPLAY, YELLOW, 4.8 mm |
| 封裝： | ROHS COMPLIANT PACKAGE-32 |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 960K |
| 代理商： | IPD2131 |
IPD2131, IPD2132, IPD2133
2006-04-04
10
Theory of Operation
The IPD213X Display is designed to work with all major micropro-
cessors. Data entry is via an eight bit parallel bus. Three bits of
address route the data to the proper digit location in the RAM.
Standard control signals like WR and CE allow the data to be writ-
ten into the display.
D0–D7 data bits are used for both Character RAM and control
word data input. A3 acts as the mode selector.
If A3=1, character RAM is selected. Then input data bit D7 will
determine whether input data bits D0–D6 is ASCII coded data
(D7=0) or UDC data (D7=1). See section on UDC Address Regis-
ter and UDC RAM“ (page 11).
For normal operation FL pin should be held high. When FL is held
low, Flash RAM is accessed to set character blinking.
The seven bit ASCII code is decoded by the Character ROM to
generate Column data. Twenty columns worth of data is sent out
each display cycle, and it takes fourteen display cycles to write into
eight digits.
The rows are multiplexed in two sets of seven rows each. The
internal timing and control logic synchronizes the turning on of
rows and presentation of column data to assure proper display
operation.
Power Up Sequence
Upon power up the display will come on at random. Thus the dis-
play should be reset on power-up. Reset will clear the Flash
RAM, Control Word Register and reset the internal counter. All
the digits will show blanks and display brightness level will be
100%.
The display must not be accessed until three clock pulses (110 s
minimum using the internal clock) after the rising edge of the reset
line.
Microprocessor Interface
The interface to a microprocessor is through the 8-bit data bus
(D0–D7), the 4-bit address bus (A0–A3) and control lines FL , CE
and WR.
To write data (ASCII/Control Word) into the display CE should be
held low, address and data signals stable and WR should be
brought low. The data is written on the low to high transition of
WR.
The Control Word is decoded by the Control Word Decode Logic.
Each code has a different function. The code for display brightness
changes the duty cycle for the column drivers. The peak LED cur-
rent stays the same but the average LED current diminishes
depending on the intensity level.
The character Flash Enable causes 2.0 Hz coming out of the
counter to be ANDED with the column drive signal to make the col-
umn driver cycle at 2.0 Hz. Thus the character flashes at 2.0 Hz.
The display Blink works the same way as the Flash Enable but
causes all twenty column drivers to cycle at 2.0 Hz thereby making
all eight digits blink at 2.0 Hz.
The Self Test function of the IC consists of two internal routines
which exercise major portions of the IC and illuminates all the
LEDs.
Clear bit clears the character RAM and writes a blank into the dis-
play memory. It however does not clear the control word.
ASCII Data or Control Word Data can be written into the display
at this point. For multiple display operation, CLK I/O must be
properly selected. CLK I/O will output the internal clock if CLK-
SEL=1, or will allow input from an external clock if CLKSEL=0.
Memory Selection
FL
A4
A3
Section of Memory
A2–A0
Data Bits Used
0X
X
Flash RAM
Character Address
D0
10
0
UDC Address Register
Don’t Care
D3–D0
10
1
UDC RAM
Row Address
D4–D0
11
1
Character RAM
Character Address
D7–D0
11
0
Control Word Register
Don’t Care
D7–D0
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| IPD2131-20 | 功能描述:LED 顯示器和配件 5x7 Yellow 0.2" 8-CHARACTER RoHS:否 制造商:Avago Technologies 顯示器類型:7 Segment 數(shù)位數(shù)量:2 字符大小:7.8 mm x 14.22 mm 照明顏色:Red 波長:628 nm 共用管腳:Common Anode 工作電壓:2.05 V 工作電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 35 C 封裝:Tube |
| IPD2132 | 功能描述:LED 顯示器和配件 5x7 Super Red 0.2", 8-CHARACTER RoHS:否 制造商:Avago Technologies 顯示器類型:7 Segment 數(shù)位數(shù)量:2 字符大小:7.8 mm x 14.22 mm 照明顏色:Red 波長:628 nm 共用管腳:Common Anode 工作電壓:2.05 V 工作電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 35 C 封裝:Tube |
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