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參數(shù)資料
| 型號： | IPD2131 |
| 元件分類： | 顯示用LED |
| 英文描述： | 5X7 DOT MATRIX DISPLAY, YELLOW, 4.8 mm |
| 封裝： | ROHS COMPLIANT PACKAGE-32 |
| 文件頁數(shù)： | 14/16頁 |
| 文件大小： | 960K |
| 代理商： | IPD2131 |
IPD2131, IPD2132, IPD2133
2006-04-04
7
Pin Description
Pin No.
Function
Description
Explanation
1
CLS
Clock Select
Selects an internal or external clock source. CLS=1 the internal clock selected
(master clock), CLS=0 then external clock selected (slave operation).
2
CLK
Clock I/O
Inputs or outputs the clock as determined by the CLS pin.
3
WR
Write
Writes data into the display when WR=0 and CE=0.
4
CE
Chip Enable
Enables the read/write access when low.
5
RST
Reset
Initializes the display; clears the Character RAM (20 Hex), Flash RAM
(00 Hex), Control Word (00 Hex) and resets the internal counters. UDC Address
Register and UDC RAM are unaffected.
6
RD
Read
Outputs data from the display when RD=0 and CE=0.
7
No Pin
—
8
9
10
11
D0
Data Bus
8 bit bidirectional data bus. Character RAM and Control Word uses D7–D0, UDC
Address Register uses D3–D0, UDC RAM uses D4–D0, and Flash RAM uses D0.
12
D1
13
D2
14
D3
15
NC
—
16
V
CC
—
Positive power supply.
17
GND
Supply
Analog ground for the LED drivers.
18
GND
Logic
Digital ground for the logic circuitry.
19
D4
Data Bus
8 bit bidirectional data bus. Character RAM and Control Word uses D7-D0, UDC
Address Register uses D3-D0, UDC RAM uses D4-D0, and Flash RAM uses D0.
20
D5
21
D6
22
D7
23
No Pin
—
24
25
26
27
FL
Flash
Accesses the Flash RAM. Address inputs, A2–A0, select the digit address while
data bit D0 sets (D0=1) or resets (D0=0) the Flash bit. A4 and A3 are ignored.
28
A0
Address Inputs
A4 and A3 select a section of the display’s memory. A2–A0 select specific locations
in the different sections. If FL is low the Flash RAM is accessed regardless of the
status of A4 and A3.
29
A1
30
A2
31
A3
32
A4
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