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參數資料
| 型號： | IP-ED8B10B |
| 元件分類： | 通信、網絡模塊及開發(fā)工具 |
| 英文描述： | Telecomm/Datacomm |
| 中文描述： | 電信/數據通信 |
| 文件頁數： | 9/11頁 |
| 文件大?。?/td> | 502K |
| 代理商： | IP-ED8B10B |
Altera Corporation
9
8b10b Encoder/Decoder MegaCore Function (ED8B10B) Data Sheet
I/O Signals
Tables 2
and
3
list the input/output signals for the encoder, and decoder.
Table 2. Encoder I/O Signals
Signal Name
Direction
Description
clk
Input
Clock. The input is latched, and the result is output on this clock. There
is a three clock cycle latency between the input and output.
Active low, reset. Asynchronously resets all registers in the core.
Command byte indicator. When high, indicates that the input is a
command byte, not a data byte.
Enable encoder signal. When high, indicates that the data currently
present on the
datain
input is to be encoded.
Idle character insert. When high, idle (K28.5) characters are inserted
when
enable
is not asserted.
Data input. This is the 8-bit input word, data or command.
Running disparity input. When
rdforce
is high, the value on this pin is
used as the current running disparity instead of the internally generated
one.
Force running disparity. When high, the
rdin
value overrides the
internally generated running disparity.
Special K character error. This signal is set high when
enable
and
kin
are high and the value on
datain
is not a valid special Kcharacter.
Data output. This is the 10-bit encoded output.
Valid signal. When high, indicates that a valid encoded word is present
on the
dataout
output.
Running disparity output. The current running disparity (after encoding
the word present on the
dataout
output).
Cascaded Running disparity. Used when encoders are cascaded.
reset_n
Input
Input
kin
enable
Input
idle_ins
Input
datain[7:0]
Input
Input
rdin
rdforce
Input
kerr
Output
dataout[9:0]
Output
Output
valid
rdout
Output
rdcascade
Output
Table 3. Decoder I/O Signals
Signal Name
Direction
Description
clk
Input
Clock. The input is latched, and the result output on this clock. There is
a three clock cycle latency between the input and output.
Active low, reset. Asynchronously resets all registers in the core.
Idle delete signal. When high, idle words (K28.5) are removed from the
stream (i.e.
valid
is set low when idle words are received).
Enable decoder signal. When high, indicates that the data currently
present on the
datain
input is to be decoded.
Data input. This is the 10-bit encoded input word.
reset_n
Input
Input
idle_del
enable
Input
datain[9:0]
Input
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