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參數(shù)資料
| 型號(hào)： | IP-ED8B10B |
| 元件分類： | 通信、網(wǎng)絡(luò)模塊及開發(fā)工具 |
| 英文描述： | Telecomm/Datacomm |
| 中文描述： | 電信/數(shù)據(jù)通信 |
| 文件頁(yè)數(shù)： | 8/11頁(yè) |
| 文件大小： | 502K |
| 代理商： | IP-ED8B10B |
8
Altera Corporation
8b10b Encoder/Decoder MegaCore Function (ED8B10B) Data Sheet
CASCADED DECODING
Two decoders can be cascaded to decode two words simultaneously. The
decoders are cascaded—in a similar fashion as the encoders—by
connecting the
rdcascade
output of the first decoder to the
rdin
input
of the second decoder, and by connecting the
rdout
output of the second
decoder to the
rdin
input of the first decoder. The
rdforce
inputs of
both decoders must be tied high.
To enable cascaded decoding, the data paths fed by the
rdin
and
rdforce
inputs are not cascaded. If these inputs are to be used in non-
cascaded decoders, they should be delayed by one clock cycle with respect
to their corresponding
datain
and
kin
inputs.
Decoding Latency
The decoder is pipelined, thus it takes two clock cycles for a character to
be decoded. The decoded value—corresponding to the value of
datain
sampled by the decoder on rising edge
n
—is output shortly after rising
edge
n+1
, and is available to be sampled on the rising edge of clock cycle
n+2
. (See
Figure 4 on page 7
).
Figure 6. Decoder Timing Diagram
clk
datain,
enable
a
b
c
d
e
f
g
a
b
c
d
a
dataout,
kout, kerr,
rdout, rderr
rdforce,
rdin
e
b
c
d
e
f
n
n+1
n+2
n+3
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