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參數(shù)資料
| 型號(hào)： | INTEL386 SXSA |
| 廠商： | Intel Corp. |
| 英文描述： | 5-V 32-Bit Fully Static Embedded Microprocessor(5V，32位完全靜態(tài)嵌入式微處理器) |
| 中文描述： | 5V的32位嵌入式微處理器完全靜態(tài)（5V的，32位完全靜態(tài)嵌入式微處理器） |
| 文件頁(yè)數(shù)： | 5/20頁(yè) |
| 文件大?。?/td> | 251K |
| 代理商： | INTEL386 SXSA |
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Intel386 SXSA EMBEDDED MICROPROCESSOR
5
2.0
PIN DESCRIPTIONS
Table 2 lists the Intel386 SXSA microprocessor pin descriptions. The following definitions are used in the pin
descriptions:
#
I
O
I/O Input and output signal.
P
Power pin.
G
Ground pin.
The named signal is active low.
Input signal.
Output signal.
Table 2. Pin Descriptions
Symbol
A23:1
Type
O
Pin
80–79, 76–72,
70, 66–64
62–58, 56–51,
18
16
Name and Function
Address Bus
outputs physical memory or port I/O addresses.
ADS#
O
Address Status
indicates that the processor is driving a valid
bus-cycle definition and address onto its pins (W/R#, D/C#,
M/IO#, BHE#, BLE#, and A23:1).
Byte High Enable
indicates that the processor is transferring
a high data byte.
Byte Low Enable
indicates that the processor is transferring
a low data byte.
Busy
indicates that the math coprocessor is busy.
CLK2
provides the fundamental timing for the device.
Data/Control
indicates whether the current bus cycle is a
data cycle (memory or I/O) or a control cycle (interrupt
acknowledge, halt, or code fetch). When D/C# is high, the bus
cycle is a data cycle; when D/C# is low, the bus cycle is a con-
trol cycle.
Data Bus
inputs data during memory read, I/O read, and
interrupt acknowledge cycles and outputs data during mem-
ory and I/O write cycles.
Error
indicates that the math coprocessor has an error condi-
tion.
Float
forces all bidirectional and output signals, including
HLDA, to a high-impedance state.
Bus Hold Acknowledge
indicates that the CPU has surren-
dered control of its local bus to another bus master.
Bus Hold Request
allows another bus master to request con-
trol of the local bus.
Interrupt Request
is a maskable input that causes the CPU
to suspend execution of the current program and then exe-
cute an interrupt acknowledge cycle.
BHE#
O
19
BLE#
O
17
BUSY#
CLK2
D/C#
I
I
O
34
15
24
D15:0
I/O
81–83, 86–90,
92–96, 99–100,
1
36
ERROR#
I
FLT#
I
28
HLDA
O
3
HOLD
I
4
INTR
I
40
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PDF描述 |
|---|---|
| intel386 SX | 32-Bit CPU With a 16-Bit External Data Bus And a 24-bit External Address Bus(帶16位內(nèi)部數(shù)據(jù)總線和24位內(nèi)部地址總線32位微處理器) |
| INTEL386 | Intel386 EX Embedded Microprocessor |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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