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參數(shù)資料
| 型號(hào)： | INTEL386 SXSA |
| 廠商： | Intel Corp. |
| 英文描述： | 5-V 32-Bit Fully Static Embedded Microprocessor(5V，32位完全靜態(tài)嵌入式微處理器) |
| 中文描述： | 5V的32位嵌入式微處理器完全靜態(tài)（5V的，32位完全靜態(tài)嵌入式微處理器） |
| 文件頁(yè)數(shù)： | 12/20頁(yè) |
| 文件大?。?/td> | 251K |
| 代理商： | INTEL386 SXSA |
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Intel386 SXSA EMBEDDED MICROPROCESSOR
12
5.0
AC SPECIFICATIONS
Table 6 lists output delays, input setup require-
ments, and input hold requirements. All AC specifi-
cations are relative to the CLK2 rising edge
crossing the 2.0V level.
Figure 5 shows the measurement points for AC
specifications. Inputs must be driven to the
indicated voltage levels when AC specifications are
measured. Output delays are specified with
minimum and maximum limits measured as shown.
The minimum delay times are hold times provided
to external circuitry. Input setup and hold times are
specified as minimums, defining the smallest
acceptable sampling window. Within the sampling
window, a synchronous input signal must be stable
for correct operation.
Outputs ADS#, W/R#, D/C#, MI/O#, LOCK#, BHE#,
BLE#, A23:A1 and HLDA change only at the
beginning of phase one. D15:0 (write cycles)
change only at the beginning of phase two.
The READY#, HOLD, BUSY#, ERROR#, PEREQ,
FLT# and D15:0 (read cycles) inputs are sampled at
the beginning of phase one. The NA#, INTR and
NMI inputs are sampled at the beginning of phase
two.
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