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參數(shù)資料
| 型號： | IMS82C55AZ |
| 廠商： | INTERSIL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | CMOS Programmable Peripheral Interface |
| 中文描述： | 24 I/O, PIA-GENERAL PURPOSE, PQCC44 |
| 封裝： | ROHS COMPLIANT, PLASTIC, MS-018AC, LCC-44 |
| 文件頁數(shù)： | 5/24頁 |
| 文件大?。?/td> | 502K |
| 代理商： | IMS82C55AZ |
5
FN6140.1
June 28, 2005
The modes for Port A and Port B can be separately defined,
while Port C is divided into two portions as required by the
Port A and Port B definitions. All of the output registers,
including the status flip-flops, will be reset whenever the
mode is changed. Modes may be combined so that their
functional definition can be “tailored” to almost any I/O
structure. For instance: Group B can be programmed in
Mode 0 to monitor simple switch closings or display
computational results, Group A could be programmed in
Mode 1 to monitor a keyboard or tape reader on an interrupt-
driven basis.
The mode definitions and possible mode combinations may
seem confusing at first, but after a cursory review of the
complete device operation a simple, logical I/O approach will
surface. The design of the 82C55A has taken into account
things such as efficient PC board layout, control signal definition
vs. PC layout and complete functional flexibility to support
almost any peripheral device with no external logic. Such
design represents the maximum use of the available pins.
Single Bit Set/Reset Feature (Figure 5)
Any of the eight bits of Port C can be Set or Reset using a
single Output instruction. This feature reduces software
requirements in control-based applications.
When Port C is being used as status/control for Port A or B,
these bits can be set or reset by using the Bit Set/Reset
operation just as if they were output ports.
Interrupt Control Functions
When the 82C55A is programmed to operate in mode 1 or
mode 2, control signals are provided that can be used as
interrupt request inputs to the CPU. The interrupt request
signals, generated from port C, can be inhibited or enabled
by setting or resetting the associated INTE flip-flop, using
the bit set/reset function of port C.
This function allows the programmer to enable or disable a
CPU interrupt by a specific I/O device without affecting any
other device in the interrupt structure.
INTE Flip-Flop Definition
(BIT-SET)-INTE is SET - Interrupt Enable
(BIT-RESET)-INTE is Reset - Interrupt Disable
NOTE: All Mask flip-flops are automatically reset during mode
selection and device Reset.
Operating Modes
Mode 0
(Basic Input/Output). This functional configuration
provides simple input and output operations for each of the
three ports. No handshaking is required, data is simply
written to or read from a specific port.
Mode 0 Basic Functional Definitions:
Two 8-bit ports and two 4-bit ports
Any Port can be input or output
Outputs are latched
Inputs are not latched
16 different Input/Output configurations possible
FIGURE 4. MODE DEFINITION FORMAT
D7 D6 D5
D4 D3 D2
D1 D0
PORT C (LOWER)
1 = INPUT
0 = OUTPUT
PORT B
1 = INPUT
0 = OUTPUT
MODE SELECTION
0 = MODE 0
1 = MODE 1
GROUP B
PORT C (UPPER)
1 = INPUT
0 = OUTPUT
PORT A
1 = INPUT
0 = OUTPUT
MODE SELECTION
00 = MODE 0
01 = MODE 1
1X = MODE 2
GROUP A
MODE SET FLAG
1 = ACTIVE
CONTROL WORD
FIGURE 5. BIT SET/RESET FORMAT
D7 D6 D5
D4 D3 D2
D1 D0
BIT SET/RESET
1 = SET
0 = RESET
BIT SELECT
0
1 2 3 4 5 6 7
0 1 0 1 0 1 0 1
0 0 1 1 0 0 1 1
0 0 0 0 1 1 1 1
BIT SET/RESET FLAG
0 = ACTIVE
CONTROL WORD
DON’T
CARE
X
X
X
B0
B1
B2
MS82C55A, MQ82C55A
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