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參數(shù)資料
| 型號： | IMISC643AYB |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | SSOP-48 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 138K |
| 代理商： | IMISC643AYB |
SC643
I
2C Clock Generator for 3 DIMM, Pentium
II Designs
Approved Product
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
Rev.1.6
6/20/97
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Page 6 of 12
SERIAL CONTROL REGISTERS (Cont.)
Byte 1: CPU, SIO, USB Clock Register (1 = enable, 0 = Stopped)
Bit
@Pup
Pin#
Description
7
1
26
48 Mhz enable/Stopped
6
1
25
24 Mhz enable/Stopped
5
1
-
0 = IC in TEST mode. 1 = normal operation.
4
x
-
Reserved
3
1
40
CPUCLK3 enable/Stopped
2
1
41
CPUCLK2 enable/Stopped
1
43
CPUCLK1 enable/Stopped
0
1
44
CPUCLK0 enable/Stopped
Byte 2: PCI Clock Register (1 = enable, 0 = Stopped)
Bit
@Pup
Pin#
Description
7x
-
Reserved
6
1
7
PCI_F / S1enable/Stopped
5
1
15
PCI5 / PS# enable/Stopped
4
1
13
PCI4 enable/Stopped
3
1
12
PCI3 enable/Stopped
2
1
11
PCI2 enable/Stopped
1
10
PCI1 / FTS enable/Stopped
0
1
8
PCI0 / S2 enable/Stopped
Byte 3: SDRAM Clock Register ( 1 = enable, 0 = Stopped )
Bit
@Pup
Pin#
Description
7
1
28
SDRAM7 enable/Stopped
6
1
29
SDRAM6 enable/Stopped
5
1
31
SDRAM5 enable/Stopped
4
1
32
SDRAM4 enable/Stopped
3
1
34
SDRAM3 enable/Stopped
2
1
35
SDRAM2 enable/Stopped
1
37
SDRAM1 enable/Stopped
0
1
38
SDRAM0 enable/Stopped
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