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參數(shù)資料
| 型號(hào)： | IMISC643AYB |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | SSOP-48 |
| 文件頁(yè)數(shù)： | 6/12頁(yè) |
| 文件大?。?/td> | 138K |
| 代理商： | IMISC643AYB |
SC643
I
2C Clock Generator for 3 DIMM, Pentium
II Designs
Approved Product
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
Rev.1.6
6/20/97
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Page 3 of 12
POWER MANAGEMENT FUNCTIONS
When MODE=0, pins 15 and 46 are inputs PS# (PCI_STOP#), and CS# (CPU_STOP#), respectively (when MODE=1,
these functions are not available). A particular output is enabled only when both the serial interface and these pins
indicate that it should be enabled. The IMISC643 clocks may be disabled according to the following table in order to
reduce power consumption. All clocks are stopped in the low state. All clocks maintain a valid high period on transitions
from running to stopped. The CPU/AGP and PCI clocks transition between running and stopped by waiting for one
positive edge on PCICLK_F followed by a negative edge on the clock of interest, after which high levels of the output are
either enabled or disabled.
CPU_STOP#
PCI_STOP#
CPU
PCI
OTHER CLKs
XTAL & VCOs
0
LOW
RUNNING
0
1
LOW
Frequency Table
RUNNING
1
0
Frequency Table
LOW
RUNNING
1
Frequency Table
RUNNING
Please note that all clocks can be individually asynchronously enabled or stopped via the 2-wire I2C control interface. In
this case all clocks are stopped in the low state.
Power Supply
VDD
PCI_F / S1
PCI0 / S2
48 MHz / S0
24 MHz / MODE
PCI1 / FTS
Hi-Z (tristate), inputs
toggle , outputs
Fig.1
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相關(guān)代理商/技術(shù)參數(shù) |
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