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參數(shù)資料
| 型號(hào)： | IMIC9806IAT |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | TSSOP-48 |
| 文件頁數(shù)： | 9/14頁 |
| 文件大?。?/td> | 221K |
| 代理商： | IMIC9806IAT |
C9806I
I
2C Frequency Clock Generator for Mobile Pentium II Applications.
Preliminary
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
Rev.1.0
4/25/2000
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Page 4 of 14
http://www.imicorp.com
2-Wire I
2C Control Interface
The 2-wire control interface implements a read/write slave only interface according to Philips I2C specification. (See
fig3). The device can be read back by using standard I
2C command bytes. Sub addressing is not supported, thus all
preceding bytes must be sent in order to change one of the control bytes. The 2-wire control interface allows each clock
output to be individually enabled or disabled. 100 Kbits/second (standard mode) data transfer is supported. It also allows
24/48 MHz frequency selection and test mode enable as well as Spread Spectrum programmability.
During normal data transfer, the SDATA signal only changes when the SCLK signal is low, and is stable when SCLK is
high. There are two exceptions to this. A high to low transition on SDATA while SCLK is high is used to indicate the
start of a data transfer cycle. A low to high transition on SDATA while SCLK is high indicates the end of a data transfer
cycle. Data is always sent as complete 8-bit bytes, after which an acknowledge is generated. The first byte of a transfer
cycle is a 7-bit address with a Read/Write bit (R/W#) as the LSB. R/W# = 1 in read mode (see note1, below). R/W# = 0
in write mode.
The device will respond to writes to 10 bytes (max) of data to address D2 by generating the acknowledge (low) signal on
the SDATA wire following reception of each byte.
If the device should be read then an address D3 must be sent. Data
is transferred MSB first at a max rate of 100kbits/S. The device will not respond to any other control interface conditions,
and previously set control registers are retained.
Fig.3
Note1: Should the device be read, the address must be D3, therefore, the address’ LSB is a 1 (for READ). After the device receives
the address it will generate an acknowledge then immediately starts outputting data on the SDATA line. Data is transmitted
following the Philips I2C standard. After each full byte is transmitted the device will wait for an acknowledge from the receiver before
transmitting the next byte. The transmission will end when the device detects a Stop condition generated by the receiver.
START
IMI Device
Master Device
STOP CONDITION
START CONDITION
IMI Device
Master Device
STOP CONDITION
1
8
ACK
MSB
00
0
SDATA
0
1
LSB
COMMAND BYTE
1
SCLK
1
BYTE N
88
8
BYTE 0
BYTE COUNT
ACK
(Don't Care)
(Valid)
Fig.3a (WRITE)
(Valid)
SDATA
1
0
(Valid)
0
11
8
BYTE N
(Valid)
BYTE COUNT
SCLK
LSB
NO ACK
8
ACK
8
0
BYTE1
1
ACK
MSB
8
1
(Valid)
BYTE 0
Fig.3b (READ)
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
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| IMIC9827H | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Clocks and Buffers |
| IMIC9827JT | 制造商:Rochester Electronics LLC 功能描述:TIMING DEVICE - Tape and Reel |
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