參數(shù)資料
型號: IMIB9940LBL
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: 時鐘及定時
英文描述: 2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer
中文描述: 9940 SERIES, LOW SKEW CLOCK DRIVER, 18 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
封裝: 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, LQFP-32
文件頁數(shù): 1/5頁
文件大?。?/td> 201K
代理商: IMIB9940LBL
2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer
B9940L
Cypress Semiconductor Corporation
Document #: 38-07105 Rev. *C
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised December 26, 2002
Features
200-MHz clock support
LVPECL or LVCMOS/LVTTL clock input
LVCMOS/LVTTL compatible inputs
18 clock outputs: drive up to 36 clock lines
150-ps max. output-to-output skew
Dual- or single-supply operation:
—3.3V core and 3.3V outputs
—3.3V core and 2.5V outputs
—2.5V core and 2.5V outputs
Pin-compatible with MPC940L
Industrial temperature range: -40°C to 85°C
32-pin LQFP package
Description
The B9940L is a low-voltage clock distribution buffer with the
capability to select either a differential LVPECL- or an
LVCMOS/LVTTL-compatible input clock. The two clock
sources can be used to provide for a test clock as well as the
primary system clock. All other control inputs are
LVCMOS/LVTTL compatible. The eighteen outputs are 2.5V or
3.3V compatible and can drive two series-terminated 50
transmission lines. With this capability the B9940L has an
effective fan-out of 1:36. Low output-to-output skews make the
B9940L an ideal clock distribution buffer for nested clock trees
in the most demanding of synchronous systems.
Block Diagram
Pin Configuration
B9940L
Q
Q
Q
V
Q
Q
Q
V
Q
Q
Q
V
Q
Q
Q
V
Q6
Q7
Q8
VDD
Q9
Q10
Q11
VSS
VSS
VSS
TCLK
TCLK_SEL
PECL_CLK
PECL_CLK#
VDD
VDDC
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
9
1
1
1
1
1
1
1
3
3
3
2
2
2
2
2
PECL_CLK
PECL_CLK#
0
1
TCLK
TCLK_SEL
VDDC
18
Q0-Q17
VDD
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IMIB9940LBLT 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer
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IMIB9947CA 制造商:Cypress Semiconductor 功能描述:Logic ICS, 3.3V, 160MHz, 1:9 Clock Distribution Buffer
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