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參數(shù)資料
| 型號： | IMIB9948CAT |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 3.3V, 160-MHz, 1:12 Clock Distribution Buffer |
| 中文描述： | 9948 SERIES, LOW SKEW CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | 7 X 7 MM, 1 MM HEIGHT, PLASTIC, QFP-32 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大?。?/td> | 100K |
| 代理商： | IMIB9948CAT |
3.3V, 160-MHz, 1:12 Clock Distribution Buffer
B9948
Cypress Semiconductor Corporation
Document #: 38-07079 Rev. *D
3901 North First Street
San Jose
CA 95134
Revised December 14, 2002
408-943-2600
Features
160-MHz clock support
LVPECL or LVCMOS/LVTTL clock input
LVCMOS/LVTTL compatible inputs
12 clock outputs: drive up to 24 clock lines
Synchronous Output Enable
Output three-state control
350-ps maximum output-to-output skew
Pin compatible with MPC948
Industrial temp. range: –40°C to +85°C
32-pin TQFP package
Description
The B9948 is a low-voltage clock distribution buffer with the
capability to select either a differential LVPECL or a LVC-
MOS/LVTTL compatible input clock. The two clock sources
can be used to provide for a test clock as well as the primary
system clock. All other control inputs are LVCMOS/LVTTL
compatible. The twelve outputs are 3.3V LVCMOS or LVTTL
compatible and can drive two series terminated 50
transmis-
sion lines. With this capability the B9948 has an effective
fan-out of 1:24. The outputs can also be three-stated via the
three-state input TS#. Low output-to-output skews make the
B9948 an ideal clock distribution buffer for nested clock trees
in the most demanding of synchronous systems.
The B9948 also provides a synchronous output enable input
for enabling or disabling the output clocks. Since this input is
internally synchronized to the input clock, potential output
glitching or runt pulse generation is eliminated.
B9948
V
Q
V
Q
V
Q
V
Q
Q
V
Q
V
Q
V
Q
V
VSS
Q4
VDDC
Q5
VSS
Q6
VDDC
Q7
TCLK_SEL
TCLK
PECL_CLK
PECL_CLK#
SYNC_OE
TS#
VDD
VSS
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
9
1
1
1
1
1
1
1
3
3
3
2
2
2
2
2
Block Diagram
Pin Configuration
PECL_CLK
PECL_CLK#
0
1
TCLK
TCLK_SEL
SYNC_OE
TS#
VDD
VDDC
12
Q0-Q11
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