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參數(shù)資料
| 型號： | IMIC9531CT |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | PCIX I/O System Clock Generator with EMI Control Features |
| 中文描述： | 133.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28 |
| 封裝： | 4.40 MM, MO-153, TSSOP-28 |
| 文件頁數(shù)： | 1/10頁 |
| 文件大?。?/td> | 115K |
| 代理商： | IMIC9531CT |
PCIX I/O System Clock Generator with EMI Control Features
C9531
Cypress Semiconductor Corporation
Document #: 38-07034 Rev. *D
3901 North First Street
San Jose, CA 95134
408-943-2600
Revised May 12, 2003
Features
Dedicated clock buffer power pins for reduced noise,
crosstalk and jitter
Input clock frequency of 25 MHz to 33 MHz
Output frequencies of XINx1, XINx2, XINx3 and XINx4
One output bank of 5 clocks.
One REF XIN clock output.
SMBus clock control interface for individual clock
disabling and SSCG control
Output clock duty cycle is 50% (± 5%)
< 250 ps skew between output clocks within a bank
Output jitter <175 ps
Spread Spectrum feature for reduced electromagnetic
interference (EMI)
OE pin for entire output bank enable control and
testability
28-pin SSOP and TSSOP packages
Note:
1.
XIN is the frequency of the clock on the device’s XIN pin.
Table 1. Test Mode Logic Table
[1]
Input Pins
S1
LOW
LOW
HIGH
HIGH
X
Output Pins
CLK
XIN
2 * XIN
3 * XIN
4 * XIN
Three-state
OE
HIGH
HIGH
HIGH
HIGH
LOW
S0
LOW
HIGH
LOW
HIGH
X
REF
XIN
XIN
XIN
XIN
Three-state
Block Diagram
Pin Configuration
XIN
CLK3
CLK4
OE
GOOD#
CLK2
CLK1
CLK0
/N
SSCG#
SSCG
Logic
1
0
XOUT
I
2
C
Control
Logic
SCLK
IA(0:2)
S(0,1)
SDATA
REF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
VDD
XOUT
VSS
S1
GOOD#
VSS
IA1
IA2
VDDA
OE
IA0
SSCG#
VSS
CLK4
VDDA
CLK3
VSS
VDDP
CLK2
CLK1
CLK0
VDDP
VSS
SCLK
SDATA
C
REF
S0
XIN
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