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參數(shù)資料
| 型號： | IMC008FLSG |
| 廠商： | INTEL CORP |
| 元件分類： | DRAM |
| 英文描述： | 5 V Series 200 Flash Memory Card(5V系列200閃速存儲器插卡) |
| 中文描述： | 8M X 8 FLASH 5V PROM CARD, 200 ns, XMA68 |
| 封裝： | PC CARD |
| 文件頁數(shù)： | 19/35頁 |
| 文件大?。?/td> | 217K |
| 代理商： | IMC008FLSG |
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E
5.2
iMC008/016/024/032/048/064FLSG
19
PRELIMINARY
Scaleable Command Set
Table 8 presents the 5 Volt Value Series 200 PC
Card’s
Scaleable Command Set Definitions
. The
table indicates that the commands require one or
more bus cycles to implement. The table and notes
following the table describe each bus cycle.
Complete descriptions of the individual commands
follow in subsections of the current document
section.
Table 8. Scaleable Command Set Definitions
(10)
Command
Bus
Cycles
Req’d.
Notes
First Bus Cycle
Second Bus Cycle
Oper
(1)
Addr
(2)
Data
(3,4)
Oper
(1)
Addr
(2)
Data
(3,4)
Read Query
≥
2
Write
X
XX98H
Read
QA
QD
Write to Buffer
> 2
5, 6, 7,
8, 9
Write
BA
XXE8H
Write
BA
N
Confirm
1
6, 7
Write
X
XXD0H
Configuration
9
NOTES:
1. Card signal values for the identified bus operations are defined in Table 3.
2. X = Any valid address within the device.
QA = QUERY database Address.
BA = Block Address.
3. QD = Data read from QUERY database.
CC = Configuration Code.
4. The upper byte of the data bus during command writes is a
“Don’t Care.”
5. After the first bus cycle of the Write to Buffer command, check the Extended Status Register to make sure the write buffer is
available for writing. If the buffer is available for writing, proceed with the second bus cycle; otherwise, continue repeating
the first bus cycle and checking the extended status register in turn until the buffer becomes available; when the buffer
becomes available, proceed with the second bus cycle of the Write to Buffer command.
6. The number of words to be written to the Write Buffer = N + 1, where N = word count argument. The word count range on
this device is N = 0000H to N = 000FH. Writing a word count outside the buffer boundary causes unexpected results and
should be avoided.
The third and consecutive bus cycles of a Write to Buffer command sequence, as determined by N, are for writing data into
the Write Buffer. In the third bus cycle a device start address is given along with the write buffer data. Subsequent write
cycles provide additional device addresses and data. All subsequent addresses must lie within the start address plus the
count. The Confirm command (XXD0H) is expected after exactly N + 1 write cycles; any other command at that point in the
sequence aborts the write to buffer operation. Please see memory component data sheet for additional information on the
Wirte to Buffer command.
7. The write buffer operation does not begin until a Confirm command is issued.
8. The issue of a Write to Buffer command to a locked block will fail.
9. The Configuration Command is not supported on the 5 Volt Value Series 200 Flash Memory PC Card. The Configuration
Command serves to program the configurable status output (STS output pin) of a memory device. To satisfy the PCMCIA
PC Card Specification the STS output pin for all card memory devices must be configured as a RY/BY# pin to generate the
card’s BUSY# output signal. At card power-up the STS output for all devices defaults to RY/BY# pin operation; thereafter,
host software shall not issue the Configuration Command.
10. Commands other than those shown above are reserved for future use and should not be used.
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