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參數(shù)資料
| 型號： | IMC008FLSG |
| 廠商： | INTEL CORP |
| 元件分類： | DRAM |
| 英文描述： | 5 V Series 200 Flash Memory Card(5V系列200閃速存儲器插卡) |
| 中文描述： | 8M X 8 FLASH 5V PROM CARD, 200 ns, XMA68 |
| 封裝： | PC CARD |
| 文件頁數(shù)： | 14/35頁 |
| 文件大?。?/td> | 217K |
| 代理商： | IMC008FLSG |
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iMC008/016/024/032/048/064FLSG
E
14
PRELIMINARY
NOTES:
1. Card signal values for the identified bus operations are defined inTable 3.
2. X = Any valid address within the device.
IA = Identifier Code Address:
BA = Address within the block being erased or locked.
WA = Address of memory location to be written.
3. SRD = Data read from Status Register.
WD = Data to be written at location WA. Data is latched on the rising edge of WE#.
ID = Data read from Identifier Codes.
4. The upper byte of the data bus during command writes is a
“Don’t Care” (X).
5. Following the Read Identifier Codes command, read operations access manufacturer, device, block lock, and master lock
codes. See Read Identifier Section for read identifier code data.
6. Either XX40H or XX10H are recognized by the WSM as the word-write command setup.
7. The issue of a block erase or write-word command to a locked block will fail.
8. The clear block lock-bits operation simultaneously clears all block lock-bits.
9. Commands other than those shown above are reserved by Intel for future device implementations and should not be used.
5.1.2
READ IDENTIFIER CODES
COMMAND
The identifier code operation is initiated by writing
the Read Identifier Codes command to a memory
device. Following the command write, read cycles
from addresses shown in Figure 2 retrieve the
manufacturer, device, block lock configuration and
master lock configuration codes (see Table 5 for
identifier code values). To terminate the operation,
write another valid command. The Read Identifier
Codes command is valid only when the WSM is off
or the device is suspended. Following the Read
Identifier Codes command, the following information
can be read:
Table 5. Identifier Codes
(1)
Code
Addr
(1)
00000
00001
00001
X
0002
(2)
Data
(00) 89
(00) 15
(00) 14
Manufacture Code
Device Code (28F640J5)
Device Code (28F320J5)
Block Lock Configuration
Block Is Unlocked
Block Is Locked
Reserved for Future Use
Master Lock Configuration
(3)
Device Is Unlocked
Device Is Locked
Reserved for Future Use
NOTES:
1.
Data is always presented on the low byte (upper byte
contains 00h).
2.
X selects the specific block’s lock configuration code.
See Figure 2 for the device identifier code memory
map.
3.
See the
5 Volt
Intel
StrataFlash Memory; 28F320J5
and 28F640J5
datasheet for a description of Master
Lock Configuration information. For 5 Volt Value Series
200 Flash Memory PC Cards the Master Lock
Configuration byte should indicate that the device is
unlocked (DQ
0
= 0).
DQ
0
= 0
DQ
0
= 1
DQ
1
–7
00003
DQ
0
= 0
DQ
0
= 1
DQ
1–7
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