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參數(shù)資料
| 型號： | IMC008FLSG |
| 廠商： | INTEL CORP |
| 元件分類： | DRAM |
| 英文描述： | 5 V Series 200 Flash Memory Card(5V系列200閃速存儲器插卡) |
| 中文描述： | 8M X 8 FLASH 5V PROM CARD, 200 ns, XMA68 |
| 封裝： | PC CARD |
| 文件頁數(shù)： | 16/35頁 |
| 文件大?。?/td> | 217K |
| 代理商： | IMC008FLSG |
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iMC008/016/024/032/048/064FLSG
E
16
PRELIMINARY
Table 6. Status Register Definitions
(1)
WSMS
ESS
ECLBS
PSLBS
VPENS
R
DPS
R
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
High Z
When
Busy
Status Register Bits
NOTES:
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
SR.7 = WRITE STATE MACHINE STATUS
1 = Ready
0 = Busy
SR.6 = ERASE SUSPEND STATUS
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
SR.5 = ERASE AND CLEAR LOCK-BITS
STATUS
1 = Error in Block Erasure or Clear Lock-Bits
0 = Successful Block Erase or Clear Lock-Bits
SR.4 = WRITE AND SET LOCK-BIT STATUS
1 = Error in Write Operation or Set
Master/Block Lock-Bit
0 = Successful Write Operation or Set
Master/Block Lock Bit
SR.3 = PROGRAMMING VOLTAGE STATUS
1 = Low Programming Voltage Detected,
Write Operation Aborted
0 = Programming Voltage OK
SR.2 = RESERVED FOR FUTURE
ENHANCEMENTS
SR.1 = DEVICE PROTECT STATUS
1 = Master Lock-Bit, Block Lock-Bit and/or
RESET# (RP#) Lock Detected, Operation
Abort
0 = Unlock
SR.0 = RESERVED FOR FUTURE
ENHANCEMENTS
Check BUSY# or SR.7 to determine block
erase, write (program), or lock-bit
configuration completion. SR.6
–SR.0 are not
driven while SR.7 = “0.”
If both SR.5 and SR.4 are “1”s after a block
erase or lock-bit configuration attempt, an
improper command sequence was entered.
SR.3 does not provide a continuous memory
device (write) programming voltage level
indication. The WSM interrogates and
indicates the programming voltage level only
after Block Erase, Word Write, Write to
Buffer, Set Block/Master Lock-Bit, or Clear
Block Lock-Bits command sequences.
SR.1 does not provide a continuous
indication of master and block lock-bit values.
The WSM interrogates the master lock-bit,
block lock-bit, and RESET# (RP#) only after
Block Erase, Write Word, Write to Buffer or
Lock-Bit configuration command sequences.
It informs the system, depending on the
attempted operation, if the block lock-bit is
set, master lock-bit is set, and/or RESET#
(RP#) is not V
HH
. Read the block lock and
master lock configuration codes using the
Read Identifier Codes command to determine
master and block lock-bit status.
SR.2 and SR.0 are reserved for future use
and should be masked when polling the
status register.
NOTE:
1. See the 5 VoltIntel
StrataFlash Memory; 28F320J5 and 28F640J5
datasheet for a description of the master lock-bit. For
5 Volt Value Series 200 Flash Memory PC Cards the master lock-bit should always be =
“0” and should not interfere with
any of the card’s write or erase operations. The bit is referenced in the table for consistency of definition between the card
and card memory device datasheets as the card status register information is actually provided by whatever memory device
receives the Read Status Register command.
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