參數(shù)資料
型號(hào)： IMC008FLSC
廠商： INTEL CORP
元件分類： DRAM
英文描述： 5 V Value Series 100 Flash Memory Card(5V 100系列閃速存儲(chǔ)器卡)
中文描述： 4M X 16 FLASH 5V PROM CARD, 100 ns, XMA68
封裝： PC CARD-68
文件頁(yè)數(shù)： 16/29頁(yè)
文件大?。?/td> 211K
代理商： IMC008FLSC
iMC002/004/008/016FLSC
E
16
PRELIMINARY
The host sets the block lock-bit using a two-cycle
command sequence. The host writes the set block
lock-bit setup command along with the appropriate
block or device address. This command is followed
by the set block lock-bit confirm command (and an
address within the block to be locked). The WSM
controls the set lock-bit algorithm. After the host
completes the command sequence, the card
automatically outputs status register data when
read. The CPU can detect the completion of the set
lock-bit event by analyzing the BUSY# pin output or
status register bit SR.7.
When the WSM completes the set lock-bit
operation, the host should check status register bit
SR.4. If the host detects an error it should clear the
status register. The CUI will remain in read status
register mode until the host issues a new
command.
This two-step sequence of set-up followed by
execution ensures that the host does not
accidentally set the lock-bits. An invalid Set Block
Lock-Bit command will result in the WSM setting
status register bits SR.4 and SR.5 to
“1.”
5.10
Clear Block Lock-Bits
Command
The host clears all set block lock-bits in parallel
using the Clear Block Lock-Bits command. The host
is free to clear block lock-bits using the Clear Block
Lock-Bits command
The host executes the clear block lock-bits
operation using a two-cycle command sequence.
The host must first issue a Clear Block Lock-Bits
setup command. This command is followed by a
confirm command. After the host completes the
two-cycle
command
sequence,
automatically outputs status register data when
read. The CPU can detect completion of the clear
block lock-bits event by analyzing the BUSY# pin
output or status register bit SR.7.
the
device
When the WSM completes the operation, the host
should check status register bit SR.5. If the host
detects a clear block lock-bit error, the host should
clear the status register. The CUI will remain in read
status register mode until the host issues another
command.
This two-step sequence of set-up followed by
execution ensures that the host does not
accidentally clear block lock-bits. An invalid Clear
Block Lock-Bits command sequence will result in
the WSM setting status register bits SR.4 and SR.5
to “1.”
If a clear block lock-bits operation is aborted due to
V
CC
transitioning out of valid range or RESET#
active transition, block lock-bit values are left in an
undetermined state. The host must repeat the clear
block lock-bits command to initialize block lock-bit
contents to known values.
6.0
PC CARD INFORMATION
STRUCTURE
The Card Information Structure (CIS) begins at
address 00000000H of the card’s Common Memory
Plane and resides sequentially in memory locations
with
even
byte memory addresses. It contains a
variable length chain of data blocks (tuples) that
conform to a basic format (Table 6). The CIS of the
Value Series 100 card is found in Table 7.
CAUTION:
The CIS data in Block 0 is not write
protected and should not be erased by the
system software if the CIS is needed for card
recognition.
Table 7. PC Card Tuple Format
Bytes
Data
0
Tuple Code: CISTPL_xxx. The tuple
code 0FFH indicates no more tuples in
the list.
1
Tuple Link: TPL_LINK. Link to the next
tuple in the list. This can be viewed as
the number of additional bytes in tuple,
excluding this byte. A link field of zero
indicates an empty tuple body. A link
field containing 0FFH indicates the last
tuple in the list.
2-n
Bytes specific to this tuple.
相關(guān)PDF資料
PDF描述
IMC016FLSC 5 V Value Series 100 Flash Memory Card(5V 100系列閃速存儲(chǔ)器卡)
IMC004FLSP 4 MegaBaytes Series 2+ Flash Memory Card(4M字節(jié)閃速存儲(chǔ)器卡)
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IMC040FLSP 40 MegaBaytes Series 2+ Flash Memory Card(40M字節(jié)閃速存儲(chǔ)器卡)
IMC020FLSP 20 MegaBaytes Series 2+ Flash Memory Card(20M字節(jié)閃速存儲(chǔ)器卡)
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