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參數(shù)資料
| 型號： | IMC008FLSC |
| 廠商： | INTEL CORP |
| 元件分類： | DRAM |
| 英文描述： | 5 V Value Series 100 Flash Memory Card(5V 100系列閃速存儲器卡) |
| 中文描述： | 4M X 16 FLASH 5V PROM CARD, 100 ns, XMA68 |
| 封裝： | PC CARD-68 |
| 文件頁數(shù)： | 15/29頁 |
| 文件大?。?/td> | 211K |
| 代理商： | IMC008FLSC |
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E
5.6
iMC002/004/008/016FLSC
15
PRELIMINARY
Erase Suspend/Erase Resume
Commands (B0B0H, D0D0H)
The Erase Suspend command allows block erase
interruption in order to read data from another block
of memory. Once the erase process starts, writing
the Erase Suspend command (B0B0H) to the CUI
requests that the WSM suspend the erase
sequences at a predetermined point in the erase
algorithm. The 28F0XXS5 continues to output
status register data when read, after the Erase
Suspend command is written to it. Polling the WSM
Status and Erase Suspend Status bits will
determine when the erase operation has been
suspended (both will be set to
“1”). RDY/BSY# will
also transition to V
OH
.
At this point, a Read Array command can be written
to the CUI to read data from blocks other than that
which is suspended. The only other valid
commands, at this time, are Read Status Register
(7070H) and Erase Resume (D0D0H), at which time
the WSM will continue with the erase process. The
Erase Suspend Status and WSM Status bits of the
status register will automatically cleared and the
RDY/BSY# will return to V
. After the Erase
Resume command is written to it, the 28F0XXS5
automatically outputs status register data when
read.
5.7
Program Commands (4040H or
1010H)
The Program command is executed by a two-
command sequence. The Program Setup command
(4040H or 1010H) is written to the CUI, followed by
a second write specifying the address and data
(latched on the rising edge of WE#) to be
programmed. The WSM then takes over, controlling
the program and program verify algorithms
internally. After the two-command write sequence is
written to it, the 28F0XXS5 automatically outputs
status register data when read. The CPU can detect
the completion of the program event by analyzing
the output of the RDY/BSY# pin, or the WSM
Status bit of the status register. Only the Read
Status Register command is valid while program is
active.
When program is complete, the Program Status bit
should be checked. If program error is detected, the
status register should be cleared. The internal WSM
verify only detects errors for “1”s that do not
successfully program to “0”s. The CUI remains in
read status register mode until further commands
are issued to it.
5.8
Word Write Suspend Command
The conversion to the 28F0XXS5 family adds the
capability to suspend a programming or word-write
operation. Once a word write operation is
suspended, the card can be read, even if the data
is located on the same component as was being
programmed.
The
command
programming is the same as the Erase suspend
command, B0B0H. The program operation can be
resumed by
issueing
command, D0D0H.
to
suspend
the
Program
resume
Once the word write process starts, writing the
Word Write Suspend command requests that the
WSM suspend the word write sequence at a
predetermined point in the algorithm. After the host
writes the Word Write Suspend command, it should
write the Read Status Register command. Polling
status register bits SR.7 and SR.2 can determine
when the WSM suspends the byte write operation
(both will be set to “1”). BUSY# will also transition to
V
. Specification t
WHRH1
defines the word write
suspend latency. It is also possible that the word
write completes before the device has an
opportunity to suspend. The host should also check
for this condition.
After the word write has been suspended, the host
can write the Read Array command to read data
from any location except the suspended location.
The only other valid commands while word write is
suspended are Read Status Register and Word
Write Resume. After the host writes a Word Write
Resume to the CUI, the WSM will continue the word
write process. Status register bits SR.2 and SR.7
will automatically clear and BUSY# will return to
V
OL
. After the host writes the Word Write Resume
command, the device automatically outputs status
register data when read.
5.9
Set Block Lock-Bit Command
The host can enable a flexible block locking and
unlocking scheme using the Set Block Lock-Bit
command. This command enables the host to lock
individual blocks within the flash array.
The block
lock-bits gate program and erase operations.
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