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參數(shù)資料
| 型號： | IMC004FLSA |
| 廠商： | Intel Corp. |
| 英文描述： | SERIES 2 FLASH MEMORY CARDS iMC002FLSA, iMC004FLSA, iMC010FLSA, iMC020FLSA |
| 中文描述： | 系列2記憶卡iMC002FLSA，iMC004FLSA，iMC010FLSA，iMC020FLSA |
| 文件頁數(shù)： | 22/39頁 |
| 文件大?。?/td> | 548K |
| 代理商： | IMC004FLSA |
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SERIES 2 FLASH MEMORY CARDS
290434–27
Bus
Command
x8 Mode
x16 Mode
Operation
Write
Suspend
Erase
Data
e
B0H,
Address
e
Desired
Block to Erase
Suspend
Data
e
B0B0H,
Address
e
Desired
Block Pair to Erase
Suspend
Read
Status Register
Data. Toggle OE
Y
,
CE
1
Y
or CE
2
Y
to
update Status
Register
Status Register
Data. Toggle OE
Y
or
(CE
1
Y
and CE
2
Y
)
to update Status
Register
Standby
Check SR Bit 7
1
e
Ready,
0
e
Busy
Check SR Bit 7 and 15
1
e
Ready,
0
e
Busy
Standby
Check SR Bit 6
1
e
Suspended,
0
e
In Progress
Check SR Bit 6 and 14
1
e
Suspended,
0
e
In Progress
Write
Rd Array
Cmd
Data
e
FFH
Data
e
FFFFH
Read
Read Data
until finished
Read Data
until finished
Write
Erase
Resume
Data
e
D0H,
Address
e
Valid
Block Address.
Data
e
D0D0H,
Address
e
Valid
Block Pair Address.
Figure 15. Erase Suspend/Resume Algorithm. Allows Reads to Interrupt Erases.
POWER CONSUMPTION
STANDBY MODE
In most applications, software will only be accessing
one device pair at a time. The Series 2 Card is de-
fined to be in the standby mode when one device
pair is in the Read Array Mode while the remaining
devices are in the Deep-Sleep Mode. The Series 2
Card’s CE
1
Y
and CE
2
Y
input signals must also be
at V
IH
. In standby mode, much of the card’s circuitry
is shut off, substantially reducing power consump-
tion. Typical power consumption for a 20 Megabyte
Series 2 card in standby mode is 65
m
A.
SLEEP MODE
Writing a ‘‘1’’ to the PWRDWN bit of the GLOBAL
POWERDOWN REGISTER places all FlashFile
Memory devices into a Deep-Sleep mode. This dis-
ables most of the 28F008SA’s circuitry and reduces
current consumption to 0.2
m
A per device. Addition-
ally, when the host system pulls ASIC control logic
high and latches all address and data lines (i.e., not
toggling), the card’s total current draw is reduced to
approximately 5
m
A (CMOS input levels) for a 20
Megabyte card. On writing a ‘‘0’’ to the PWRDWN bit
(Global PowerDown Register) or any individual de-
vice pair (Sleep Control Register), a Deep-Sleep
mode
recovery
period
28F008SA device circuitry to power back on.
must
be
allowed
for
22
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相關(guān)代理商/技術(shù)參數(shù) |
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