參數(shù)資料
型號: IMC004FLSA
廠商: Intel Corp.
英文描述: SERIES 2 FLASH MEMORY CARDS iMC002FLSA, iMC004FLSA, iMC010FLSA, iMC020FLSA
中文描述: 系列2記憶卡iMC002FLSA,iMC004FLSA,iMC010FLSA,iMC020FLSA
文件頁數(shù): 21/39頁
文件大?。?/td> 548K
代理商: IMC004FLSA
SERIES 2 FLASH MEMORY CARDS
290434–19
Bus
Command
x8 Mode
x16 Mode
Operation
Write
Erase
Setup
Data
e
20H
Address
e
Block
Within Card to be
Erased
Data
e
2020H
Address
e
Block Pair
Within Card to be
Erased
Write
Erase
Data
e
D0H
Address
e
Block
Within Card to be
Erased
Data
e
D0D0H
Address
e
Block
Pair Within Card to
be Erased
Read
Defaults to
Device Sta- Data. Toggle OE
Y
,
tus Register CE
1
Y
or CE
2
Y
to
Read Mode
update Status
Status Register
Status Register
Data. Toggle OE
Y
or
(CE
1
Y
and CE
2
Y
)
to update Status
Register
Register
Standby
Check SR Bit 7
1
e
Ready,
0
e
Busy
Check SR Bits 7 and 15
1
e
Ready,
0
e
Busy
FULL STATUS CHECK PROCEDURE
290434–20
Bus
Command
x8 Mode
x16 Mode
Operation
Standby
Check SR Bit 3
1
e
V
PP
Detected
Low
Check SR Bits
3 and 11
Either Bit 1
e
V
PP
Detected Low
Standby
Check SR Bits 4 and 5 Check SR Bits 4, 5,
Both 1
e
Command
Sequence Error
12, 13
All 1
e
Command
Sequence Error
Standby
Check SR Bit 5
1
e
Block Erase
Error
Check SR Bits
5 and 13
Both 1
e
Block
Erase Failure
Figure 14. Device-Level Automated Erase Algorithm
NOTES:
1. Repeat for subsequent data writes.
2. In addition, the card’s READY-BUSY STATUS REGISTER or the RDY/BSY
Y
pin may be used.
3. Full device-level status check can be done after each block erase or after a sequence of block erases.
4. Write FFH (or FFFFH) after the last block erase operation to reset the device(s) to Ready Array Mode.
5. If a block erase operation fails due to a low V
PP
(setting SR Bit 3), the Clear Status Register command MUST be issued
before further attempts are allowed by the Write State Machine.
6. If a block erase operation fails during a multiple block erase sequence, SR Bit 4 (Write Status) will not be cleared until the
Command User Interface receives the Clear Status Register command.
21
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