參數(shù)資料
型號(hào): IFM016G
廠商: INTEL CORP
元件分類(lèi): DRAM
英文描述: 5 V Series 200 Flash Memory Miniature Card(5V 200系列閃速存儲(chǔ)器微型卡)
中文描述: 1M X 16 FLASH 5V PROM CARD, 150 ns, XMA60
文件頁(yè)數(shù): 12/35頁(yè)
文件大?。?/td> 262K
代理商: IFM016G
iFM004G/iFM008G/iFM016G
E
12
PRELIMINARY
Reserved for Future
Implementation
Reserved for Future
Implementation
(Blocks 32 through 62)
Reserved for Future
Implementation
Reserved for Future
Implementation
(Blocks 2 through 30)
Reserved for Future
Implementation
Reserved for Future
Implementation
Block 63
Block 31
Block 1
Block 0 Lock Configuration
Device Code
Reserved for Future
Implementation
Block 0
Master Lock Configuration
Manufacturer Code
3FFFFF
3F0003
3F0002
3F0000
3EFFFF
1EFFFF
1F0003
1F0002
1F0000
01FFFF
010003
010002
010000
00FFFF
000004
000003
000002
000001
000000
3
6
Word
Address
A[22-1]: 64 Mbit
A[21-1]: 32 Mbit
Block 31 Lock Configuration
Block 63 Lock Configuration
Block 1 Lock Configuration
0606_06
NOTES:
1.
Data is always given on the low byte (upper byte
contains 00h).
Memory shown is accessed by the Read Identifier
Codes command only and is physically distinct from
the card’s flash memory array.
Master Lock function of the card’s underlying memory
devices is not a card function. The Master Lock
Configuration information identified in the above
memory map is shown only for the sake of
consistency between the illustrated memory map and
a corresponding memory map shown in the datasheet
for the memory devices.
2.
3.
Figure 3. Device Identifier Code Memory Map
4.1.5
READ IDENTIFIER CODES
The read identifier codes operation outputs the
manufacturer code, device code, block lock
configuration codes for each block, and the master
lock configuration code (see Figure 3) Using the
manufacturer and device codes, the system CPU
can automatically match the device with its proper
algorithms. The block lock and master lock
configuration codes identify locked and unlocked
blocks and master lock-bit setting.
4.1.6
WRITE
Writing commands to the CUI enables reading of
device data, query, identifier codes, inspection and
clearing of the status register, as well as block
erasure, writing of data and lock-bit configuration.
The Block Erase command requires appropriate
command data and an address within the block to
be erased. The Word Write command requires the
command and address of the location to be written.
The Write to Buffer command requires the
command, starting address of the memory region to
be written and the number of words to be written to
the write buffer. Set Master and Block Lock-Bit
commands require the command and address
within the device (Master Lock) or block within the
device (Block Lock) to be locked. The Clear Block
Lock-Bits command requires the command and
address within the device.
The CUI does not occupy an addressable memory
location. It is part of each memory device and is
written when the device is enabled and WE# is
active. The address and data needed to execute a
command are latched on the rising edge of WE# or
the first edge of CEL# or CEH# that disables the
device. Write cycle timing is specified in Section 9.2
(Write Operations).
4.2
Decode Logic
The card’s decode logic enables the appropriate
memory component during a read or write access
of card memory. Unused upper addresses for the
5 Volt Series 200 Miniature Card will not be
decoded. The address decoding will wrap around at
the card’s density.
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