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參數(shù)資料
| 型號： | IFM016G |
| 廠商： | INTEL CORP |
| 元件分類： | DRAM |
| 英文描述： | 5 V Series 200 Flash Memory Miniature Card(5V 200系列閃速存儲器微型卡) |
| 中文描述： | 1M X 16 FLASH 5V PROM CARD, 150 ns, XMA60 |
| 文件頁數(shù)： | 11/35頁 |
| 文件大?。?/td> | 262K |
| 代理商： | IFM016G |
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E
NOTES:
1.
X can be V
IL
or V
IH
for control signals and address.
2.
BUSY# is V
when the WSM is executing internal write or block erase algorithms. It is V
OH
when the WSM is not busy, in
erase suspend mode, or deep power-down mode.
3.
The device code can be 14H, or 15H.
Software should check for both cases for compatibility with future cards.
4.
High indicates high byte data, low indicates low byte data.
5.
Both memory bytes will be read from memory as the card’s memory component data bus is word-wide and does not
provide for individual byte access. The bus operation is non-compliant with the
PCMCIA PC Card Standard
as the
PC
Card Standard
specifies a byte read operation instead of a word read operation for the listed signal conditions.
6.
Both memory bytes will be written to memory as the card’s memory component data bus is word-wide and does not
provide for individual byte access. The bus operation is non-compliant with the
PCMCIA PC Card Standard
as the
PC
Card Standard
specifies a byte write operation instead of a word write operation for the listed signal conditions. If a host
system desires a byte write operation instead of a word write operation, then the host system must write VH to the
unwanted active byte (which should be inactive according the
PC Card Standard
) in order to prevent the unwanted active
byte from being written to card memory.
iFM004G/iFM008G/iFM016G
11
PRELIMINARY
4.1.3
STANDBY
If both CEL# and CEH# are at a logic-high level
(V
), the card enters standby mode. Standby
operation disables much of the card’s circuitry and
substantially reduces device power consumption.
The outputs (D
0
–D
15
) are placed in a high-
impedance state independent of the status of OE#.
If the host deselects the card during a write or
erase, the card continues to function and consume
normal active power until the operation completes.
4.1.4
RESET/POWER-DOWN
RESET# at V
IL
initiates the reset/power-down
mode.
In read modes, RESET#-low deselects the card’s
memory, places output drivers in a high-impedance
state, and turns off numerous internal memory
circuits. RESET# must be held low for a minimum
of t
w
. Time t
su
is required after return from reset
mode until initial memory access outputs are valid.
After this wake-up interval, normal operation is
restored. The CUI is reset to read array mode and
all memory device status registers are set to 80H.
During block erase, write, or lock-bit configuration
modes, RESET#-low will abort the operation
BUSY# transitions low and remains low for a
maximum time of t
w
+ t
su
until the reset operation is
complete. Memory contents being altered are no
longer valid; the data may be partially corrupted
after a write operation or partially altered after an
erase or lock-bit configuration operation. Time t
su
is
required after RESET# goes to logic-high (V
IH
)
before another command can be written.
As with any automated device, it is important to
assert RESET# during system reset. When the
system comes out of reset, it expects to read data
from the flash memory. Automated flash memories
provide status information when accessed during
block erase, write, or lock-bit configuration modes.
If a CPU reset occurs with no flash memory reset,
proper initialization may not occur because the
flash memory may be providing status information
instead of array data. Intel
Flash memories allow
proper initialization following a system reset through
the use of the RESET# input. In this application,
RESET# is controlled by the same signal that
resets the system CPU.
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