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參數(shù)資料
| 型號(hào)： | IDTCSPF2510C |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | 3.3V PHASE-LOCK LOOP CLOCK DRIVER |
| 中文描述： | 3.3鎖相環(huán)時(shí)鐘驅(qū)動(dòng)器 |
| 文件頁(yè)數(shù)： | 4/8頁(yè) |
| 文件大小： | 68K |
| 代理商： | IDTCSPF2510C |
4
0oC TO 85oC TEMPERATURE RANGE
IDTCSPF2510C
3.3V PHASE-LOCK LOOP CLOCK DRIVER
DC ELECTRICAL CHARACTERISTICS OV ER OPERATING FREE-AIR TEMPERA-
T URE RANGE (UNLES S OT HERWIS E NOT ED)
Symbol
V
IH
V
IL
V
IK
Test Conditions
Input HIGH Level
Input LOW Level
I
I
= -18mA
I
OH
= -100
μ
A
I
OH
= -12mA
I
OH
= -6mA
I
OL
= 100
μ
A
I
OL
= 12mA
I
OL
= 6mA
V
I
= V
DD
or GND
V
I
= V
DD
or GND, AV
DD
= GND, I
O
= 0, Outputs: LOW or HIGH
One input at V
DD
- 0.6V, other inputs at V
DD
or GND
Power Dissipation Capacitance
V
DD
3V
Min.
2
V
DD
– 0.2
2.1
2.4
Typ.
10
Max.
0.8
– 1.2
0.2
0.8
0.55
±5
10
500
14
Unit
V
V
V
Mn. to Max.
3V
3V
Mn. to Max.
3V
3V
3.6V
3.6V
3.3V to 3.6V
3.6V
V
OH
V
V
OH
V
I
I
μ
A
μ
A
μ
A
pF
I
DD
I
DD
C
PD
I
DDA
(2)
AV
DD
Power Supply Current
AV
DD
= 3.3V
10
mA
NOTES:
1. For conditions shown as Min. or Max., use the appropriate value specified under recommended operating conditions.
2. For I
DD
of AV
DD
, see TYPICAL CHARACTERISTICS.
OPERATING FREE-AIR TEMPERATURE
Min.
25
40%
Max.
140
60%
1
Unit
MHz
Clock frequency
Input clock duty cycle
Stabilization time
(1)
f
CLOCK
ms
TIMING REQUIREMENTS OV ER OPERATING RANGE OF SUPPLY VOLTAGE AND
NOTE:
1. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency, fixed-phase
reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew and jitter parameters given in the switching characteristics
table are not applicable.
SWITCHING CHARACTERISTICS OV ER OPERATING RANGE OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, C
L
= 25pF
V
DD
= 3.3V ± 0.165V
Min.
Typ.
– 50
1.3
1.7
V
DD
= 3.3V ± 0.3V
Typ.
|
70
|
|
65
|
Parameter
(1)
t
PHASE
error
(2)
t
PHASE
error – jitter
(2,4)
t
SK(o)
(3)
Jitter (cycle-cycle)
(peak-to-peak)
Duty cycle reference
(5)
t
R
t
F
From (Input)
100MHz < CLK
↑
< 133MHz
CLK
↑
= 133MHz
Any Y (133MHz)
CLK = 66MHz to 133MHz
CLK = 100MHz to 133MHz
CLK = 133MHz
To (Output)
FBIN
↑
FBIN
↑
Any Y
Any Y or FBOUT
Any Y or FBOUT
Any Y or FBOUT
Any Y or FBOUT
Any Y or FBOUT
Max.
50
1.9
2.5
Min.
– 150
45
0.8
0.8
Max.
150
150
55
2.1
2.5
Unit
ps
ps
ps
ps
ps
%
ns
ns
NOTES:
1.
2.
3.
4.
5.
The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.
See PARAMETER MEASUREMENT INFORMATION.
The t
SK(O)
specification is only valid for equal loading of all outputs.
Phase error does not include jitter.
See TYPICAL CHARACTERISTICS.
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| IDTCSPF2510CPG | 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:3.3V PHASE-LOCK LOOP CLOCK DRIVER |
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