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參數(shù)資料
| 型號： | IDTCV107E |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | CLP SINE |
| 中文描述： | 時鐘發(fā)生器的臺式機平臺 |
| 文件頁數(shù)： | 1/21頁 |
| 文件大?。?/td> | 96K |
| 代理商： | IDTCV107E |
COMMERCIAL TEMPERATURE RANGE
IDTCV107E
CLOCK GENERATOR FOR DESKTOP PC PLATFORMS
1
J ANUARY 2004
COMME RCIAL T E MPE RAT URE RANGE
XTAL
Osc Amp
SM Bus
Controller
Watch Dog
Timer
Logic
OCPU CLK
AGP/PCI
Output Buffers
SRC CLK
Output Buffer
48MHz
Output Buffer
X1
X2
SDATA
SCLK
V
TT_PWRGD
FS[1:0]
S
EL
24_48#
I
REF
I
REF
CPU[1:0]
REF 2.1.0
PCI[5:0], PCIF[2:0]
3V66[3:0]
SRC
48MHz[1:0]
24 - 48MHz
PLL3
SSC
PLL4
PLL1
SSC
EasyN
Programming
PLL2
SSC
EasyN
Programming
RESET#
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2004 Integrated Device Technology, Inc.
DSC-6390/14
FUNCTIONAL BLOCK DIAGRAM
OUTPUT TABLE
CPU (Pair)
2
3V66
3
3V66/VCH
1
PCI
6
PCIF
3
REF
3
48MHz
2
24 - 48MHz
1
SRC (Pair)
1
Reset#
1
IDTCV107E
CLOCK GENERATOR FOR
DESKTOP PC PLATFORMS
FEATURES:
4 PLL architecture
Linear frequency programming
Independent frequency programming and SSC control
Band-gap circuit for differential output
High power-noise rejection ratio
66MHz to 533MHz CPU frequency
VCO frequency up to 1.1G
Support index block read/write, single cycle index block read
Programmable REF, 3V66, PCI, 48MHz I/O drive strength
Programmable 3V66 and PCI Skew
Available in SSOP package
DESCRIPTION:
IDTCV107E is a 48 pin clock generation device for desktop PC platforms.
This chip incorporates four PLLs to allow independent generation of CPU, AGP/
PCI, SRC, and 48MHz clocks. The dedicated PLL for Serial ATA clock
provides high accuracy frequency. This device also implements Band-gap
referenced I
REF
to reduce the impact of V
DD
variation on differential outputs,
which can provide more robust systemperformance.
Static PLL frequency divide error can be as low as 36 ppm providing high
accuracy output clock. Each CPU, AGP/PCI, SRC clock has its own Spread
Spectrumselection.
K EY SPECIFICATION:
CPU/SRC CLK cycle to cycle jitter < 125ps
SATA CLK cycle to cycle jitter < 125ps
PCI CLK cycle to cycle jitter < 250ps
Static PLL frequency divide error as low as 36 ppm
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDTCV107EPVG | 功能描述:IC CLK GEN DESKTOP PC 48-SSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| IDTCV107EPVG8 | 功能描述:IC CLK GEN DESKTOP PC 48-SSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| IDTCV109E | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:CLOCK GENERATOR FOR DESKTOP PC PLATFORMS |
| IDTCV109EPV | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:CLOCK GENERATOR FOR DESKTOP PC PLATFORMS |
| IDTCV110JP | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR |
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