參數(shù)資料
型號： IDT82V3358EDG
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 100/139頁
文件大小： 0K
描述： IC PLL WAN SYNC ETHERNET 64TQFP
標(biāo)準(zhǔn)包裝： 160
類型： 時鐘/頻率發(fā)生器，多路復(fù)用器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum
輸入： CMOS，LVDS，PECL
輸出： CMOS，LVDS，PECL
電路數(shù)： 1
比率 - 輸入:輸出： 2:4
差分 - 輸入:輸出： 是/是
頻率 - 最大： 622.08MHz
電源電壓： 3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 64-TQFP-EP（10x10）
包裝： 托盤
IDT82V3358
SYNCHRONOUS ETHERNET WAN PLL
Programming Information
63
May 19, 2009
INTERRUPTS3_STS - Interrupt Status 3
INTERRUPTS1_ENABLE_CNFG - Interrupt Control 1
Address: 0FH
Type: Read / Write
Default Value: 11X1XXXX
Bit
Name
Description
7
EX_SYNC_ALARM
This bit indicates whether an external sync alarm is raised; i.e., whether there is a transition from ‘0’ to ‘1’ on the
EX_SYNC_ALARM_MON bit (b7, 52H).
0: Has not occurred.
1: Has occurred. (default)
This bit is cleared by writing a ‘1’.
6T4_STS
This bit indicates the T4 DPLL locking status changes (from ‘locked’ to ‘unlocked’ or from ‘unlocked’ to ‘locked’); i.e., whether
there is a transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the T4_DPLL_LOCK bit (b6, 52H).
0: Has not changed.
1: Has changed. (default)
This bit is cleared by writing a ‘1’.
5
-
Reserved.
4INPUT_TO_T4
This bit indicates whether all the input clocks for T4 path changes to be unqualified; i.e., whether the
HIGHEST_PRIORITY_VALIDATED[3:0] bits (b7~4, 4EH) are set to ‘0000’ when these bits are available for T4 path.
0: Has not changed.
1: Has changed. (default)
This bit is cleared by writing a ‘1’.
3 - 0
-
Reserved.
Address: 10H
Type: Read / Write
Default Value: XX0000XX
Bit
Name
Description
7 - 6
-
Reserved.
5 - 4
INn_DIFF
This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when the input clock validity changes (from
‘valid’ to ‘invalid’ or from ‘invalid’ to ‘valid’), i.e., when the corresponding INn_DIFF bit (b5/4, 0DH) is ‘1’. Here n is 2 or 1.
0: Disabled. (default)
1: Enabled.
3 - 2
INn_CMOS
This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when the input clock validity changes (from
‘valid’ to ‘invalid’ or from ‘invalid’ to ‘valid’), i.e., when the corresponding INn_CMOS bit (b3/2, 0DH) is ‘1’. Here n is 2 or 1.
0: Disabled. (default)
1: Enabled.
1 - 0
-
Reserved.
7
6543210
EX_SYNC_ALARM
T4_STS
-
INPUT_TO_T4
-
76543210
-
IN2_DIFF
IN1_DIFF
IN2_CMOS
IN1_CMOS
-
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT82V3358EDG8 制造商:Integrated Device Technology Inc 功能描述:IC PLL WAN SYNC ETHERNET 64TQFP
IDT82V3380 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:SYNCHRONOUS ETHERNET WAN PLL
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