參數(shù)資料
型號(hào)： IDT82V3280PFG
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 99/171頁
文件大?。?/td> 0K
描述： IC PLL WAN SE STRATUM 2 100-TQFP
標(biāo)準(zhǔn)包裝： 1
類型： 時(shí)鐘/頻率發(fā)生器，多路復(fù)用器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum
輸入： CMOS，LVDS，PECL
輸出： CMOS，LVDS，PECL
電路數(shù)： 1
比率 - 輸入:輸出： 14:9
差分 - 輸入:輸出： 是/是
頻率 - 最大： 622.08MHz
電源電壓： 3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-TQFP（14x14）
包裝： 托盤
其它名稱： 82V3280PFG
IDT82V3280
WAN PLL
Functional Description
33
December 9, 2008
The causes of Item 4, 9, 12, 15 - ‘the T0 selected input clock is
switched to another one’ - are: (The T0 selected input clock is disquali-
fied AND Another input clock is switched to) OR (In Revertive switch, a
qualified input clock with a higher priority is switched to) OR (The T0
selected input clock is switched to another one by External Fast selec-
tion or Forced selection).
Refer to Table 13 for details about the input clock qualification for T0
path.
3.9.2
T4 SELECTED INPUT CLOCK VS. DPLL OPERATING
MODE
The T4 DPLL operating mode is controlled by the
T4_OPERATING_MODE[2:0] bits, as shown in Table 16:
When the operating mode is switched automatically, the operation of
the internal state machine is shown in Figure 8:
Figure 8. T4 Selected Input Clock vs. DPLL Automatic
Operating Mode
Notes to Figure 8:
1. Reset.
2. An input clock is selected.
3. (The T4 selected input clock is disqualified) OR (A qualified input
clock with a higher priority is switched to) OR (The T4 selected
input clock is switched to another one by Forced selection) OR
(When T4 DPLL locks to the T0 DPLL output, the T4 selected
input clock is switched by setting the T0_FOR_T4 bit).
4. An input clock is selected.
5. No input clock is selected.
Refer to Table 13 for details about the input clock qualification for T4
path.
Table 16: T4 DPLL Operating Mode Control
T4_OPERATING_MODE[2:0]
T4 DPLL Operating Mode
000
Automatic
001
Forced - Free-Run
010
Forced - Holdover
100
Forced - Locked
2
Locked mode
Holdover
mode
Free-Run mode
1
3
4
5
Table 17: Related Bit / Register in Chapter 3.9
Bit
Register
Address
(Hex)
T0_OPERATING_MODE[2:0] T0_OPERATING_MODE_CNFG
53
T4_OPERATING_MODE[2:0] T4_OPERATING_MODE_CNFG
54
T0_DPLL_OPERATING_MOD
E[2:0]
OPERATING_STS
52
T0_DPLL_LOCK
T0_OPERATING_MODE 1
INTERRUPTS2_STS
0E
T0_OPERATING_MODE 2
INTERRUPTS2_ENABLE_CNFG
11
T0_FOR_T4
T4_INPUT_SEL_CNFG
51
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參數(shù)描述
IDT82V3280PFG8 功能描述:IC PLL WAN SE STRATUM 2 100-TQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT
IDT82V3280PFGBLANK 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL
IDT82V3285 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL
IDT82V3285AEQG 功能描述:IC PLL WAN SE STRATUM 100TQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT
IDT82V3285AEQG8 制造商:Integrated Device Technology Inc 功能描述:IC PLL WAN SE STRATUM 100TQFP
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